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TNETV2685FIBZUT7 数据表(PDF) 130 Page - Texas Instruments |
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TNETV2685FIBZUT7 数据表(HTML) 130 Page - Texas Instruments |
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130 / 191 page  Peripheral ConfigurationBus Interruptand DMA Requests 16-BitShiftRegister 16-BitBuffer 16-BitEmulationBuffer GPIO Control (allpins) State Machine Clock Control SPIDO SPIDI SPICSx SPICLK SLAVE SPI MASTER SPI SPIDO SPIDI SPICLK Optional − Slave Chip Select SPICSx SPICSx SPICLK SPIDO SPIDI TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com 6.14 Serial Peripheral Interface Port (SPI) 6.14.1 SPI Device-Specific Information Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate only as a master, in which case, it initiates a transfer and drives the SPICLK pin. Four clock phase and polarity options are supported as well as many data formatting options. Figure 6-34. Block Diagram of SPI Module The SPI supports 3- and 4-pin operation with three basic pins (SPICLK, SPIDO, and SPIDI) and two optional pins (SPICSx). The optional SPICSx (Slave Chip Select) pin is most useful to enable in master mode when there are more than one slave devices on the same SPI port. The device only shifts data and drives the SPIDI pin when SPICSx is held low. Figure 6-35. Illustration of SPI Master-to-SPI Slave Connection 130 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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