TNETV2685FIBZUT7 datasheet(131/191 Pages) TI1

131 / 191 page

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.14.2 SPI Peripheral Register Descriptions

Table 6-60 is a list of the SPI registers.

Table 6-60. SPI Configuration Registers

SPI0

DESCRIPTION

BYTE ADDRESS

0x0204 7800

SPIGCR0

Global Control Register 0

0x0204 7804

SPIGCR1

Global Control Register 1

0x0204 7808

SPIINT0

Interrupt Register

0x0204 780C

SPILVL

Interrupt Level Register

0x0204 7810

SPIFLG

Flag Register

0x0204 7814

SPIPC0

Pin Control Register 0 (Pin Function)

0x0204 7818

SPIPC1

Pin Control Register 1 (Pin Direction)

0x0204 781C

SPIPC2

Pin Control Register 2 (Pin Data In)

0x0204 783C

SPIDAT1

Shift Register 1 (with format select)

0x0204 7840

SPIBUF

Buffer Register

0x0204 7844

SPIEMU

Emulation Register

0x0204 7848

SPIDELAY

Delay Register

0x0204 784C

SPIDEF

Default Chip Select Register

0x0204 7850

SPIFMT0

Format Register 0

0x0204 7854

SPIFMT1

Format Register 1

0x0204 7858

SPIFMT2

Format Register 2

0x0204 785C

SPIFMT3

Format Register 3

0x0204 7860

TGINTVECT0

Interrupt Vector for SPI INT0

0x0204 7864

TGINTVECT1

Interrupt Vector for SPI INT1

Peripheral Information and Electrical Specifications

131

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