TNETV2685FIBZUT9 datasheet(24/191 Pages) TI1

24 / 191 page

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

Table 2-4. Terminal Functions (continued)

TERMINAL NAME

TYPE(

INTERNAL

OPER

DESCRIPTION

PULLUP/

VOLT

PULLDOWN

CONFIGURATION AND EMIFA

DEVICEENABLE0/

I/O/Z

IPD

3.3 V

EMIFA External Address 20 (word address). (O/Z) For proper

AEA20

device operation, this pin must be externally pulled up with a 1-k

Ω

resistor at device reset

EMIFAWIDTH/

I/O/Z

IPD

3.3 V

EMIFA External Address 22 (word address). (O/Z) EMIFA data

AEA22

bus width selection pin state captured at the rising edge of

RESET.

0 - sets EMIFA CS2 to 8-bit data bus width

1 - sets EMIFA CS2 to 16 bit data bus width. For details, see

Section 3.

FASTBOOT/

I/O/Z

IPD

3.3 V

EMIFA External Address 22 (word address). (O/Z) Enables FAST

AEA21

BOOT of the device. For details, see Section 3.

UHPIEN

IPD

3.3 V

UHPI Enable Pin. This pin controls the selection (enable/disable)

of the HPI and GPIO[0:7] muxed with PCI. For details, see

Section 3.

HPIWIDTH/

I/O/Z

IPD

3.3 V

EMIFA External Address 16 (word address) (O/Z) HPI peripheral

AEA16

bus width (HPI_WIDTH) select (Applies only when HPI is enabled;

UHPIEN pin = 1)

RSV_BOOT/

I/O/Z

IPU

3.3 V

EMIFA External Address 15 (word address) (O/Z) For proper

AEA15

device operation, this pin must be externally pulled up with a 1-k

Ω

resistor at device reset.

PCI66/AEA18

I/O/Z

IPD

3.3 V

PCI Frequency Selection (PCI66). The PCI peripheral must be

enabled (UHPIEN = 0) to use this function. PCI66_AEA18 selects

the PCI operating frequency of 66 MHz or 33 MHz. PCI operating

frequency is selected at reset via the pullup/pulldown resistor on

the PCI66 pin AEA18:

0 - PCI operates at 33 MHz (default)

1 - PCI operates at 66 MHz.

BOOTMODE0/AEA11

I/O/Z

IPD

3.3 V

The BOOTMODE[3:0] defines what boot code is executed on

BOOTMODE1/AEA12

device reset. See Section 3.2.1 for more details.

BOOTMODE2/AEA13

BOOTMODE3/AEA14

INTER-INTEGRATED CIRCUIT (I2C)

SCL

D22

I/O/Z

3.3 V

I2C clock. When the I2C module is used, use an external pullup

resistor.

SDA

C23

I/O/Z

3.3 V

I2C data. When I2C is used, make certain there is an external

pullup resistor.

SGMII0/1 and MDIO(1)(2)

SGMII0RXN

AA10

1.2 V

Differential SGMII Port 0 RX input (negative)

SGMII0RXP

AA9

1.2 V

Differential SGMII Port 0 RX input (positive)

SGMII0TXN

W11

1.2 V

Differential SGMII Port 0 TX output (negative)

SGMII0TXP

Y11

1.2 V

Differential SGMII Port 0 TX output (positive)

SGMII1RXN

AC9

1.2 V

Differential SGMII Port 1 RX input (negative)

SGMII1RXP

AB9

1.2 V

Differential SGMII Port 1 RX input (positive)

SGMII1TXN

1.2 V

Differential SGMII Port 1 TX output (negative)

SGMII1TXP

1.2 V

Differential SGMII Port 1 TX output (positive)

MDCLK

IPD

3.3 V

MDIO Serial Clock (MDCLK)

(1)

For DM647: Leave the SGMII1RXP/N and SGMII1TXP/N pins disconnected. Disable ENTX/ENRX bits in CFGTX1/CFGRX1 for SGMII1

and still configure the CFGPLL because the SerDes TXBCLK0 is used as the internal VBUS clock. For DM648: if one of the SGMII pair

is not used, the same approach must be used.

(2)

If the Ethernet Subsystem is not used at all, these connections must be followed:

•

Disconnect AA10, AA9, W11,Y11, AC9, AB9, W9, W8, and U9

•

Connect AC11 to CVDD

•

Connect AB11 to VSS

•

Directly connect V11 (VDDA), W10 (VDDA), T10 (VDDD), U10 (VDDD) , AB8 (VDDT), U11 (VDDT), R9 (ESS core power), R11 (ESS core

power) to CVDD

•

Directly connect AB10, (VDDR) to DVDD18

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