TNETV2685FIBZUT9 datasheet(67/191 Pages) TI1

67 / 191 page

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

Table 6-6. PLL1 Clock Frequency Ranges

CLOCK SIGNAL

MIN

MAX

UNIT

CLKIN1

66.6

MHz

PLLREF (PLLEN = 1)(1)

66.6

MHz

PLLOUT (1)

400

720 (-720 devices)

MHz

400

800 (-800 devices)(2)

MHz

400

900 (-900 devices)

MHz

400

1100 (-1100 devices)

MHz

SYSCLK4

1/16P(3)

PLLOUT/ (2*(PLLDIV4.RATIO+1))(4)

MHz

(1)

Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register). Based on CLKIN1 and PLLOUT, PLL1

multiplier factor ranges from x16 to x32.

(2)

Only for Extended Temperature Range device (-800 MHz)

(3)

P = 1/CPU clock frequency in ns

(4)

PLLDIV4.RATIO =3

6.4.2

PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is

determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is

generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In

bypass mode, CLKIN1 is fed directly to SYSREFCLK.

All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is

changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration

has completed.

6.4.3

PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device power-up. The PLL should not be operated until this stabilization time has

finished.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1) for the

PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time

value, see Table 6-7.

Table 6-7. PLL1 Stabilization, Lock, and Reset Times

MIN

TYP

MAX

UNIT

PLL stabilization time

150

μs

PLL lock time

2000 × C(1)

μs

PLL reset time

128 × C(1)

μs

(1)

C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

Peripheral Information and Electrical Specifications

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