TNETV2685FIBZUT9 datasheet(95/191 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

Table 6-24. Timing Requirements for Reset(1) (2) (see Figure 6-10) (continued)

720, 800, 900, 1100

NO.

UNIT

MIN

MAX

Hold time, boot mode and configuration pins valid after POR high or RESET

th(boot)

high (4)

Table 6-25. Switching Characteristics Over Recommended Operating Conditions During Reset(1)

(see Figure 6-10)

720, 800, 900, 1100

NO.

PARAMETER

UNIT

MIN

MAX

td(PORH-RSTATH)

Delay time, POR high AND RESET high to RESETSTAT high

1500C

(1)

C = 1/CLKIN1 clock frequency in ns.

•

Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high

impedance as soon as their respective power supply has reached normal operating conditions. Pins

remain in high impedance until configured otherwise by their respective peripherals.

•

Low group consists of pins that become low as soon as their respective power supply has reached

normal operating conditions. Pins remain low until configured otherwise by their respective peripheral.

•

High group consists of pins that become high as soon as their respective power supply has reached

normal operating conditions. Pins remain high until configured otherwise by their respective peripheral.

•

All peripherals must be enabled through software following a power-on reset; for more details, see

Section 6.7.1, Power-on Reset.

•

For power-supply sequence requirements, see Section 6.3.1.

RESET should be used only after the device has been powered up. For more details on the use of the RESET pin,

see Section 6.7, Reset Controller.

A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the

RESET pin during a Warm Reset.

Boot and Device Configuration Inputs (during reset) include AEA[22:11], and UHPIEN.

Figure 6-10. Warm Reset and Max Reset Timing

Peripheral Information and Electrical Specifications

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