TNETV2685FIBZUT9 datasheet(85/191 Pages) TI1

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TMS320DM647

TMS320DM648

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SPRS372H – MAY 2007 – REVISED APRIL 2012

device initialization is also started.

4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,

PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of

both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their

respective system reference clocks. After the pause, the system clocks are restarted at their default

divide-by settings.

The device is now out of reset; device execution begins as dictated by the selected boot mode.

6.7.2

Warm Reset (RESET Pin)

A warm reset has the same effect as a power-on reset, except that in this case, the test and emulation

logic are not reset.

The following sequence must be followed during a warm reset:

1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the low period of the RESET pin,

the following occurs:

(a) The Z-group pins, low-group pins, and the high-group pins are set to their reset state

(b) The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules

that use reset asynchronously

registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock. The PLL1

controller clocks start running at the frequency of the system reference clock. The clocks are

propagated throughout the chip to reset modules that use reset synchronously.

(d) The RESETSTAT pin becomes active (low), indicating the device is in reset.

2. The RESET pin may now be released (driven inactive high). When the RESET pin is released, the

configuration pin values are latched and the PLL controllers immediately change their system clocks to

their default divide-down values. Other device initialization is also started.

After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are

allowed to finish their current cycles and then paused for 10 cycles of their respective system reference

clocks. After the pause the system clocks are restarted at their default divide-by settings.

The clock and reset of each peripheral is determined by the default settings of the PSC.

The device is now out of reset, device execution begins as dictated by the selected boot mode.

6.7.3

Maximum Reset

A maximum (max) reset is initiated by the emulator. The effects are the same as a warm reset, except the

device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the

ICEPICK module. This ICEPICK initiated reset is nonmaskable.

The max reset sequence is as follows:

1. Max reset is initiated by the emulator. During this time, the following happens:

(a) The reset signals flow to the entire chip, resetting all the modules on chip except the test and

emulation logic.

(b) The PLL controllers are reset, PLL1 switches back to PLL bypass mode, resetting all their registers

to default values. Both PLL1 and PLL2 are placed in reset and lose lock.

2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the

end of these 10 cycles, the RESETSTAT pin is deasserted (driven high). At this point, the following

occurs:

(a) The I/O pins are controlled by the default peripherals (default peripherals are determined by

PINMUX register).

(b) The clock and reset of each peripheral is determined by the default settings of the power and sleep

controller (PSC).

Peripheral Information and Electrical Specifications

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