TNETV2685FIBZUT9 datasheet(69/191 Pages) TI1

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PLLV2

C162

C161

EMIFilter

+1.8V

560pF

0.1 F

PLL2

CLKIN2

PLLM

x20

PLLOUT

PLLREF

DDR2MemoryController

SYSCLK1(FromPLL Controller1)

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.5

PLL2 Controller

The secondary PLL controller generates interface clocks for the DDR2 memory controller.

As shown in Figure 6-7, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed

to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external

PLL filter circuit must be added to PLLV2 as shown in Figure 6-7. The 1.8-V supply for the EMI filter must

be from the same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter

manufacturer Murata, part number NFM18CC222R1C3.

Figure 6-7. PLL Controller

All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+

DSP device as possible. For the best performance, TI requires that all the PLL external components be on

a single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For

the input clock timing requirements, see Section 6.5.3, PLL2 Controller Input Clock Electrical Data/Timing.

6.5.1

PLL2 Controller Device-Specific Information

As shown in Figure 6-7, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This

clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that,

internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1

controller.

Note that there is a minimum and maximum operating frequency for PLLREF and PLLOUT. The clock

generator must not be configured to exceed any of these constraints. For the PLL clocks input and output

frequency ranges, see Table 6-10.

Table 6-10. PLL2 Clock Frequency Ranges

CLOCK SIGNAL

REQUIRED FREQUENCY

UNIT

PLLREF (CLKIN2 )

20 - 26.6

MHz

PLLOUT (DDR2 clock)

400 - 533(1)

MHz

(1)

This clock is the 2x of the DDR clock. The DDR PHY divides the clock down /2.

Peripheral Information and Electrical Specifications

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