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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2 数据表(PDF) 253 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 253 Page - STMicroelectronics |
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253 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 253/371 Figure 118. PWM generator block diagram Functional description The three PWM signals are generated using a free-running 12-bit PWM counter and three 13-bit compare registers for phase U, V and W: MCMPU, MCMPV and MCMPW registers respectively. A fourth 12-bit register is needed to set-up the PWM carrier frequency: MCMP0 register. Each of these compare registers is buffered with a preload register. Transfer from preload to active registers is done synchronously with PWM counter underflow or overflow depending on configuration. This allows compare values to be written without risks of spurious PWM transitions. The block diagram of the PWM generator is shown in Figure 118. Prescaler The 12-bit PWM counter clock is supplied through a 3-bit prescaler to allow the generation of lower PWM carrier frequencies. It divides Fmtc by 1, 2, 3, ..., 8 to get Fmtc-pwm. This prescaler is accessed through three bits PCP[2:0] in MPCR register; this register is buffered: the new value is taken into account after a PWM update event. MREP register 12-bit compare 0 register 12-bit PWM counter 13-bit compare W register up to 16MHz CMS bit 13-bit compare U register 13-bit compare V register U U U U Clear up/down Prescaler PCP[2:0] bits U Reg U event Update of compare registers PWM Notes Preload registers transferred to active registers on U event Fmtc MPCR register MPCR register interrupt generation Repetition counter Obsolete Product(s) - Obsolete Product(s) |
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