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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2 数据表(PDF) 255 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 255 Page - STMicroelectronics |
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255 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 255/371 Figure 120. Center-aligned PWM waveforms (compare 0 register = 8) Edge-aligned mode (CMS bit = 0) In this operating mode, the PWM counter counts up to the value loaded in the 12-bit compare register. Then the PWM counter is cleared and it restarts counting up. The PWM signals are set to ‘0’ when the PWM counter reaches, in up-counting, the corresponding 13-bit Compare register value and they are set to ‘1’ when the PWM counter is cleared. If the 13-bit compare register value is greater than the extended compare 0 register (the 13th bit is set to ‘0’), the corresponding PWM output signal is held at ‘1’. If the 13-bit compare register value = 0, the corresponding PWM output signal is held at ‘0’. Figure 121 shows some edge-aligned PWM waveforms in an example where the compare 0 register value = 8. 0123 456 7 8765 4321 01 1 2 3‘1’ 4‘0’ 1 compare register value = 4 2 compare register value = 7 3 compare register value ≥ 8 4 compare register value = 0 Obsolete Product(s) - Obsolete Product(s) |
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