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ST7MC1K2 数据表(PDF) 256 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 256 Page - STMicroelectronics |
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256 / 371 page ![]() Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 256/371 Figure 121. Edge-aligned PWM waveforms (compare 0 register = 8) 12-bit mode (PMS bit = 0 in the MPCR register) This mode is useful for MCMP0 values ranging from 9 bits to 12 bits. Figure 122 presents the way compare 0 and compare U, V, W should be loaded. It requires loading two bytes in the MCMPxH and MCMPxL registers (that is, MCMP0, MCMPU, MCMPV and MCMPW 16- bit registers) following the sequence described below: ● write to the MCMPxL register (LSB) first ● then write to the MCMPxH register (MSB). The 16-bit value is then ready to be transferred in the active register as soon as an update event occurs. This sequence is necessary to avoid potential conflicts with update interrupts causing the hardware transfer from preload to active registers: if an update event occurs in the middle of the above sequence, the update is effective only when the MSB has been written. 8-bit PWM mode (PMS bit = 1 in MPCR register) This mode is useful whenever the MCMP0 value is less than or equal to 8-bits. It allows significant CPU resource savings when computing three-phase duty cycles during PWM interrupt routines. In this mode, the compare 0 and compare U, V, W registers have the same size (8 bits). The extension of the MCMPx registers is done in using the OVFx bits in the MPCR register (refer to Figure 122). These bits force the related duty-cycles to 100% and are reset by hardware on occurence of a PWM update event. Note: Read access to registers with preload: During read accesses, values read are the content of the preload registers, not the active registers. Note: Compare register active bit locations: The 13 active bits of the MCMPx registers are left- aligned. This allows temporary calculations to be done with 16-bit precision, round-up is done automatically to the 13-bit format when loading the values of the MCMPx registers. Note: MCMP0x registers: The configuration MCMP0H = MCMP0L = 0 is not allowed. 01234567 801 1 2 3‘1’ 4‘0’ 1 compare register value = 4 2 compare register value = 8 3 compare register value > 8 Obsolete Product(s) - Obsolete Product(s) |
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