STM32F042F4 datasheet(23/117 Pages) STMICROELECTRONICS

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STM32F042x4 STM32F042x6

Functional overview

TIM16 and TIM17 have a complementary output with dead-time generation and

independent DMA request generation.

Their counters can be frozen in debug mode.

3.12.3

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

operates independently from the main clock, it can operate in Stop and Standby modes. It

can be used either as a watchdog to reset the device when a problem occurs, or as a free

running timer for application timeout management. It is hardware or software configurable

through the option bytes. The counter can be frozen in debug mode.

3.12.4

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

3.12.5

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•

a 24-bit down counter

•

autoreload capability

•

maskable system interrupt generation when the counter reaches 0

•

programmable clock source (HCLK or HCLK/8)

3.13

Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either

on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit

registers used to store 20 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset, or at wake up from Standby mode.

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