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STM32F401CD 数据表(PDF) 108 Page - STMicroelectronics |
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STM32F401CD 数据表(HTML) 108 Page - STMicroelectronics |
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108 / 135 page  Electrical characteristics STM32F401xD STM32F401xE 108/135 The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 67. ADC accuracy at fADC = 18 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Guaranteed by characterization, not tested in production. Unit ET Total unadjusted error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±3 ±4 LSB EO Offset error ±2 ±3 EG Gain error ±1 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±2 ±3 Table 68. ADC accuracy at fADC = 30 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Guaranteed by characterization, not tested in production. Unit ET Total unadjusted error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±4 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 Table 69. ADC accuracy at fADC = 36 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Guaranteed by characterization, not tested in production. Unit ET Total unadjusted error fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±4 ±7 LSB EO Offset error ±2 ±3 EG Gain error ±3 ±6 ED Differential linearity error ±2 ±3 EL Integral linearity error ±3 ±6 |
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