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STM32F769AI 数据表(PDF) 135 Page - STMicroelectronics |
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STM32F769AI 数据表(HTML) 135 Page - STMicroelectronics |
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135 / 255 page ![]() DocID029041 Rev 4 135/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 224 On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • I/O compensation cell enabled. • The ART/L1-cache is ON. • Scale 1 mode selected, internal digital voltage V12 = 1.32 V. • HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with only one peripheral clocked on –fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2), fHCLK = 144 MHz (Scale 3) • Ambient operating temperature is 25 °C and VDD=3.3 V. IDDIO I/O switching Current CEXT = 22 pF C = CINT + CS + CEXT 2 0.3 0.1 mA 8 1.0 0.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - CEXT = 33 pF C = CINT + CS + CEXT 2 0.3 0.2 8 1.3 0.7 25 3.5 2.3 50 10.26 5.19 60 16.53 - 1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF. Table 38. Switching output I/O current consumption(1) (continued) Symbol Parameter Conditions I/O toggling frequency (fsw) MHz Typ VDD = 3.3 V Typ VDD = 1.8 V Unit |
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