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STM32F769AI 数据表(PDF) 201 Page - STMicroelectronics |
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STM32F769AI 数据表(HTML) 201 Page - STMicroelectronics |
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201 / 255 page  DocID029041 Rev 4 201/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 224 Figure 64. Asynchronous multiplexed PSRAM/NOR write waveforms Table 106. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 4THCLK 14THCLK + 1 ns tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK 1THCLK + 0.5 tw(NWE) FMC_NWE low time 2THCLK 0.5 2THCLK+ 0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK 0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5 tw(NADV) FMC_NADV low time THCLK THCLK+ 1 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) THCLK 0.5 - th(A_NWE) Address hold time after FMC_NWE high THCLK + 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK 0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK + 0.5 - |
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