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PC87334VLJ 数据表(PDF) 21 Page - National Semiconductor (TI) |
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PC87334VLJ 数据表(HTML) 21 Page - National Semiconductor (TI) |
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21 / 102 page  20 Configuration Registers (Continued) TABLE 2-1 Default Configurations Controlled by Hardware (Continued) Configuration Pins (CFGn) (Hex) Data Activated Functions 43210 FER e 49 C9 FDC IDE ll PORT PTR e 00 80 Power-Down Clocks Option 10000 FAR e 00 PRI PRI LPTB 10001 FAR e 01 PRI PRI LPTA 10010 FAR e 01 PRI SEC LPTA 10011 FAR e 00 PRI SEC LPTB FER e 07 UART1 UART2 ll PORT PTR e 00 80 Power-Down Clocks Option 10100 FAR e 10 COM1 COM2 LPTB 10101 FAR e 11 COM1 COM2 LPTA 10110 FAR e 39 COM3 COM4 LPTA 10111 FAR e 24 COM2 COM3 LPTB FER e 47 C7 IDE UART1 UART2 ll PORT PTR e 00 80 Power-Down Clocks Option 11000 FAR e 10 PRI COM1 COM2 LPTB 11001 FAR e 11 PRI COM1 COM2 LPTA 11010 FAR e 11 SEC COM1 COM2 LPTA 11011 FAR e 39 PRI COM3 COM4 LPTA 11100 FAR e 24 PRI COM2 COM3 LPTB 11101 FAR e 38 SEC COM3 COM4 LPTB FER e 08 FDC PTR e 00 80 Power-Down Clocks Option 11110 FAR e 10 PRI FER e 00 None PTR e 02 82 Power-Down XTAL and Clocks 11111 FAR e 10 NA 21 |
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