PC87334VLJ datasheet(40/102 Pages) NSC

40 / 102 page

40 FDC Command Set Description (Continued)

414 Invalid Command

If an invalid command (illegal Opcode byte in the Command

Phase) is received by the controller the controller responds

with ST0 in the Result Phase The controller does not gen-

erate an interrupt during this condition Bits 6 and 7 in the

MSR are both set to a 1 indicating to the mP that the con-

troller is in the Result Phase and the contents of ST0 must

be read The system reads an 80h value from ST0 indicating

an invalid command was received

Command Phase

Invalid Op Codes

Execution Phase

None

Result Phase

Status Register 0 (80h)

415 Lock Command

The Lock command allows the user full control of the FIFO

parameters after a software reset If the LOCK bit is set to 1

then the FIFO THRESH and PRETRK bits in the Configure

command are not affected by a software reset In addition

the FWR FRD and BST bits in the Mode command are

unaffected by a software reset If the LOCK is 0 (default

after a hardware reset) then the above bits are set to their

default values after a software reset This command is use-

ful if the system designer wishes to keep the FIFO enabled

and retain the other FIFO parameter values (such as

THRESH) after a software reset

After the command byte is written the result byte must be

read before continuing to the next command The execution

of the Lock command is not performed until the result byte

is read by the mP If the part is reset after the command byte

is written but before the result byte is read then the Lock

command execution is not performed This is done to pre-

vent accidental execution of the Lock command

Command Phase

LOCK0010100

Execution Phase

Internal Lock register is written

Result Phase

000LOCK0000

416 Mode Command

This command is used to select the special features of the

controller The bits for the Command Phase bytes are

shown in Section 41 Command Set Summary and their

function is described below These bits are set to their de-

fault values after a hardware reset The default value of

each bit is denoted by a ‘‘bullet’’ to the left of each item The

value of each parameter after a software reset is explained

Command Phase

TMR

IAF

IPS

LOW PWR

ETR

FWR

FRD

BST

R255

DENSEL

BFR

WLD

Head Settle

Execution Phase

Internal registers are written

Result Phase

None

TMR

Motor Timer mode Default after a software reset

0 e Timers for motor on and motor off are defined

for Mode 1 (See Specify command)

1 e

Timers for motor on and motor off are defined

for Mode 2 (See Specify command)

IAF

Index Address Format Default after a software reset

0 e The controller formats tracks with the Index Ad-

dress Field included (IBM and Perpendicular for-

mat)

1 e

The controller formats tracks without including

the Index Address Field (ISO format)

IPS

Implied Seek Default after a software reset

0 e The implied seek bit in the command byte of a

read write scan or verify is ignored Implied

seeks could still be enabled by the EIS bit in the

Configure command

1 e

The IPS bit in the command byte of a read write

scan or verify is enabled so that if it is set the

controller performs seek and sense interrupt op-

erations before executing the command

LOW

PWR

Low Power mode Default after a software reset

00 e Completely disable the low power mode

01 e

Automatic low power For 500 kbps operation

go into low power mode 512 ms after the head

unload timer times out For 250 kbps operation

the timeout period is doubled to 1s

10 e

Manual low power Go into low power mode

now

11 e

Not used

ETR

Extended Track Range Default after a software re-

set

0 e Track number is stored as a standard 8-bit value

compatible with the IBM ISO and Perpendicular

formats This allows access of up to 256 tracks

during a seek operation

1 e

Track number is stored as a 12-bit value The

upper four bits of the track value are stored in

the upper four bits of the head number in the

sector Address Field This allows access of up to

4096 tracks during a seek operation With this bit

set an extra byte is required in the Seek Com-

mand Phase and Sense Interrupt Result Phase

FWR

FIFO Write Disable for mP write transfers to control-

ler Default after a software reset if LOCK is 0 If

LOCK is 1 FWR retains its value after a software

reset

Note

This bit is only valid if the FIFO is enabled in the Configure

command If the FIFO is not enabled in the Configure com-

mand then this bit is a don’t care

0 e Enable FIFO mP write transfers druing the Exe-

cution Phase use the internal FIFO

1 e

Disable FIFO All write data transfers take place

without the FIFO

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