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PC87334VLJ 数据表(PDF) 17 Page - National Semiconductor (TI) |
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PC87334VLJ 数据表(HTML) 17 Page - National Semiconductor (TI) |
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17 / 102 page  10 Pin Description (Continued) Symbol PQFP TQFP IO Function Pin Pin WP Normal 36 34 I Write Protect This input indicates that the floppy disk in the selected drive is write protected Mode WP PPM 92 90 I Write Protect This pin provides an additional Write Protect signal in PPM Mode when PNF e 0 (See PD2 and Table 7-5 for further information) Mode WRITE 95 93 O Write Strobe This signal is used in EPP mode as a write strobe It is active low (See STB and Table 7-5 for further information) X1OSC 7 5 I Crystal1Clock One side of an external 24 MHz48 MHz crystal is attached here The other side of the crystal is connected to X2 If a crystal is not used a TTL or CMOS compatible clock is connected to this pin X2 8 6 O Crystal2 One side of an external 24 MHz48 MHz crystal is attached here The other side of the crystal is connected to X1OSC This pin is left unconnected if an external clock is used ZWS 31 O Zero Wait State This pin is the Zero Wait State open drain output pin when bit 6 of FCR is 0 ZWS is driven low when the EPP or ECP is written and the access can be shortened This pin is PWDN when bit 6 of FCR is 1 (See the PWDN pin for further information) TABLE 1-2 SIR Pin Allocation PQFP Pin TQFP Pin Notes No SIR SIR on UART2 SIR on IDE SIR on IDE BIT 32 of Bits 32 of IRC Bits 32 of IRC Bits 32 of IRC IRC are 00 are 01 are 10 are 11 MODEM MODEM SIR MODEM SIR MODEM SIR Bit0of Bit0of Bit0of Bit0of Bit0of Bit0of Bit0of IRC is X IRC is 0 IRC is 1 IRC is 0 IRC is 1 IRC is 0 IRC is 1 IDE 56 54 1 IDEHI VLD0 DRID13F3RD IRTX e 0 IRTX IRTX e 1 IRTX Pins 59 57 1 IOCS16 DRID0IDEACK IRRX e 0 IRRX UART2 62 60 RI2 RI2 RI2 e 1 RI2 RI2 e 1 RI2 RI2 e 1 Pins 63 61 DTR2 IRTX e 0 IRTX DTR2 DTR2 DTR2 DTR2 64 62 CTS2 CTS2 CTS2 e 0 CTS2 CTS2 e 0 CTS2 CTS2 e 0 65 63 2 SOUT2 SOUT2 SOUT2 e 1 SOUT2 SOUT2 e 1 SOUT2 SOUT2 e 1 68 66 3 DSR2 IRRX e 1 IRRX DSR2 DSR2 DSR2 DSR2 In e 0In e 0In e 0In e 0 69 67 DCD2 DCD2 DCD2 e 1 DCD2 DCD2 e 1 DCD2 DCD2 e 1 Note 1 When bits 32 of IRC are 11 the remaining configuration bits are ignored The value of DRID01 and IOCS16 are undefined and the PC87334VLJVJG assumes IDEAK e 1 when IRRX is configured Note 2 Pin is SOUT2BOUT2 Only SOUT2 is driven high in SIR mode (not BOUT) Note 3 In e 0 refers to UART2’s DSR2 input not to the IRRX input pin 17 |
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