 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PC87334VLJ 数据表(PDF) 14 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87334VLJ 数据表(HTML) 14 Page - National Semiconductor (TI) |
|
|
14 / 102 page  10 Pin Description (Continued) Symbol PQFP TQFP IO Function Pin Pin IRQ5 98 96 IO Interrupt 5 Active high output that indicates a parallel port interrupt When enabled this bit follows the ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is TRI-STATE This pin is IO only when ECP is enabled and IRQ5 is configured For ECP operation refer to the interrupt ECP Section 7111 IRQ6 97 95 O Interrupt 6 Active high output to signal the completion of the execution phase for certain FDC commands Also used to signal when a data transfer is ready during a Non-DMA operation When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode IRQ6 is always enabled and bit D3 of the DOR is reserved IRQ7 96 94 IO Interrupt 7 Active high output that indicates a parallel port interrupt When enabled this bit follows the ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is TRI-STATE This pin is IO only when ECP is enabled and IRQ7 is configured For ECP operation refer to the interrupt ECP Section 7111 IRRX 59 68 57 66 I Infrared Receive One of these pins (see Table 1-1 for pin allocation) is the infrared serial data input (See DSR2 IOCS16 DRID0 and IDEACK for further information) IRTX 56 63 54 61 O Infrared Transmit One of these pins (see Table 1-1 for pin allocation) is the infrared serial data output (See DTR2 VLD1 IDEHI VLD0 DRID1 and 3F3RD for further information) MR 2 100 I Master Reset Active high input that resets the controller to the idle state and resets all disk interface outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock command parameters are cleared to their default values The Specify command parameters are not affected The Configuration Registers are set to their selected default values MFM 53 51 IO MFM (Modified Frequency Modulation) During a chip reset when lDENT is low this pin is sampled to select the PS2 mode (MFM high) or the Model 30 mode (MFM low) An internal pull-up or external pull-down 10k resistor selects between the two PS2 modes When the PC-AT mode is desired (lDENT high) MFM should be left pulled high internally MFM reflects the current data encoding format when RESET is inactive MFM e high Defaults to low after a chip reset (See IOCHRDY for further information) MTR01 Normal 46 43 44 41 O Motor Select 01 These are the motor enable lines for drives 0 and 1 and they are controlled by bits D7 – D4 of the Digital Output register They are active low outputs They Mode are encoded with information to control four FDDs when bit 4 of the Function Enable Register (FER) is set MTR0 exchanges logical motor values with MTR1 when bit 4 of FCR is set (See DR01) MTR1 PPM 84 82 O Motor Select 1 This pin provides an additional Motor Select 1 signal in PPM Mode when PNF e 0 This pin is the motor enable line for drive 1 when bit 4 of FCR is 0 It is the motor Mode enable line for drive 0 when bit 4 of FCR is 1 This signal is active low (See BUSY and Table 7-5 for further information) MSEN01 Normal 52 51 50 49 I Media Sense These pins are Media Sense input pins when bit 0 of FCR is 0 Each pin has a 10 kX internal pull-up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins Mode and the pull-up resistors are disabled (See DRATE01 for further information) MSEN01 PPM 88 86 86 84 I Media Sense These pins provide additional Media Sense signals for PPM Mode and PNF e 0 (See PD5 7 and Table 7-5 for further information) Mode PD 45 43 O Power-Down This pin is PD output when bit 4 of PMC is 1 It is DR1 when bit 4 of PMC is 0 PD is active high whenever the FDC is in power-down state either via bit 6 of DSR (or bit 3 of FER or bit 0 of PTR) or via the mode command See DR1 for further information PD0 – 7 94 – 91 92 – 89 IO Parallel Port Data These bidirectional pins transfer data to and from the peripheral data bus and the parallel port Data Register These pins have high current drive capability (See 89–86 87–84 DC Electrical Characteristics) (See MSEN01 INDEX TRK0 WP RDATA DSKCHG and Table 7-5 for further information) 14 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
