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PC87334VLJ 数据表(PDF) 67 Page - National Semiconductor (TI) |
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PC87334VLJ 数据表(HTML) 67 Page - National Semiconductor (TI) |
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67 / 102 page  60 Serial Ports (Continued) Bit 6 This bit is the Break Control bit It causes a break condition to be transmitted to the receiving UART When it is set to 1 the serial output (SOUT) is forced to the Spacing state (0) The break is disabled by set- ting bit 6 to 0 The Break Control bit acts only on SOUT and has no effect on the transmitter logic Note that this feature enables the CPU to alert a terminal If the following sequence is used no erroneous characters will be transmitted because of the break 1 Wait for the transmitter to be idle (TEMTe1) 2 Set break for the appropriate amount of time If the transmitter will be used to time the break duration then check that TEMTe1 before clearing the Break Control bit 3 Clear break when normal transmission has to be restored During the break the Transmitter can be used as a character timer to accurately establish the break dura- tion by sending characters and monitoring THRE and TEMT Bit 7 This bit is the Divisor Latch Access Bit (DLAB) It must be set high (logic 1) to access the Divisor Latches of the Baud rate Generator during a Read or Write opera- tion or to have the Baud Out (BOUT) signal appear on the BOUT pin It must be set low (logic 0) to access any other register TABLE 6-2 PC87334 Register Summary for an Individual UART Channel No Bit Register Address A0–2e0 A0–2e0 A0–2e1 22 3 4 5 6 7 A0–2e0 A0–2e1 DLABe0 DLABe0 DLABe0 DLABe1 DLABe1 Receiver Transmitter Interrupt Register Enable Interrupt FIFO Register Control Line Register MODEM Control Register Status Line Register MODEM Status Register Scratch Pad Divisor (LSB) Latch Divisor (MSB) Latch Buffer Holding Ident Control Register Register Register Register (Read (Write (Read (Write Only) Only) Only) Only) RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM 0 Data Bit 0 Data Bit 0 Enable ‘‘0’’ if FIFO Word Data Data Delta Bit 0 Bit 0 Bit 8 (Note 1) Received Interrupt Enable Length Terminal Ready Clear Data Pending Select Ready (DR) to Send Available Bit 0 (DTR) Interrupt 1 Data Bit 1 Data Bit 1 Enable Interrupt RCVR Word Request Overrun Delta Bit 1 Bit 1 Bit 9 Transmitter ID FIFO Length to Send Error Data Holding Bit Reset Select (RTS) (OE) Set Register Bit 1 Ready Interrupt Empty 2 Data Bit 2 Data Bit 2 Enable Interrupt XMIT Number of Out 1 Parity Trailing Bit 2 Bit 2 Bit 10 Receiver ID FIFO Stop Bits Bit Error Edge Ring Line Status Bit Reset (Note 3) (PE) Indicator Interrupt 3 Data Bit 3 Data Bit 3 Enable Interrupt Reserved Parity IRQ Framing Delta Bit 3 Bit 3 Bit 11 MODEM ID Enable Enable Error Data Status Bit (FE) Carrier Interrupt (Note 2) Detect 4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Loop Break Clear to Bit 4 Bit 4 Bit 12 Select Interrupt Send (BI) (CTS) 5 Data Bit 5 Data Bit 5 0 0 Reserved Stick 0 Transmitter Data Bit 5 Bit 5 Bit 13 Parity Holding Set Register Ready (THRE) (DSR) 6 Data Bit 6 Data Bit 6 0 FIFOs RCVR Set 0 Transmitter Ring Bit 6 Bit 6 Bit 14 Enabled Trigger Break Empty Indicator (Note 2) (MSB) (TEMT) (RI) 7 Data Bit 7 Data Bit 7 0 FIFOs RCVR Divisor 0 Error in Data Bit 7 Bit 7 Bit 15 Enabled Trigger Latch RCVR Carrier (Note 2) (MSB) Access Bit FIFO Detect (DLAB) (Note 2) (DCD) Note 1 Bit 0 is the least significant bit It is the first bit serially transmitted or received Note 2 These bits are always 0 in the NS16450 Mode Note 3 This bit no longer has a pin associated with it 67 |
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