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HT66F4530 数据表(PDF) 127 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 127 Page - Holtek Semiconductor Inc |
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127 / 224 page  Rev. 1.00 1�� De�e��e� �1� �01� Rev. 1.00 1�7 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers SAINS[2:0] SACS[3:0] Input Signals Description 000� 101~111 0000~0111 AN0~AN7 Exte�nal pin analog input 1000~1111 — Non-existed channel, input is floating. 001 1000~1111 VBGREF Inte�nal high pe�fo��an�e Bandgap �efe�en�e voltage 010 1000~1111 OPA0O Internal SD operational amplifier 0 output signal 011 1000~1111 OPA1O Internal SD operational amplifier 1 output signal 100 1000~1111 GND Unused� �onne�ted to g�ound A/D Converter Input Signal Selection – HT66F4540/HT66F4550 VBGRC Register Bit 7 6 5 4 3 2 1 0 Na�e — — — — — — — VBGREN R/W — — — — — — — R/W POR — — — — — — — 0 Bit7~1 Unimplemented,readas"0" Bit0 VBGREN:Bandgapenableordisablecontrol 0:Disable 1:Enable WhentheVBGRENbitisclearedtozero,theVBGREFisinahighimpedancestate. Conversion Rate and Timing Diagram AcompleteA/Dconversioncontainstwoparts,datasamplinganddataconversion.Thedata samplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/D clockcycles.Thereforeatotalof16A/DclockcyclesforanexternalinputA/Dconversionwhichis definedastADCarenecessary. MaximumsingleA/Dconversionrate=A/Dclockperiod/16 Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigital conversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiated bytheapplicationprogram,themicrocontrollerinternalhardwarewillbegintocarryoutthe conversion,duringwhichtimetheprogramcancontinuewithotherfunctions.Thetimetakenforthe A/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod. ADCEN START ADBZ SACS[3:0] (SAINS[�:0]=000) off on off on tON�ST tADS A/D sa�pling ti�e tADS A/D sa�pling ti�e Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion End of A/D �onve�sion End of A/D �onve�sion tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e 0011B 0010B 0000B 0001B A/D �hannel swit�h A/D Conversion Timing |
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