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HT66F4530 数据表(PDF) 125 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 125 Page - Holtek Semiconductor Inc |
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125 / 224 page  Rev. 1.00 1�4 De�e��e� �1� �01� Rev. 1.00 1�5 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselect 000:fSYS 001:fSYS/2 010:fSYS/4 011:fSYS/8 100:fSYS/16 101:fSYS/32 110:fSYS/64 111:fSYS/128 ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter. A/D Converter Operation TheSTARTbitintheSADC0registerisusedtostarttheADconversion.Whenthemicrocontrollersets thisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated. TheADBZbitintheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversion processisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteran A/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZwillbe clearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterrupt controlregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbe generated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/D internalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontroller canpolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternative methodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe SACKS2~SACKS0bitsintheSADC1register.AlthoughtheA/Dclocksourceisdeterminedbythe systemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/D clocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod, tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,asthe systemclockoperatesatafrequencyof8MHz,theSACKS2~SACKS0bitsshouldnotbesetto000, 001or111.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/Dclockperiod whichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples, wherevaluesmarkedwithanasterisk*showwhere,dependinguponthesedevices,specialcare mustbetaken,asthevaluesmaybelessorlargerthanthespecifiedminimumA/DClockPeriod. fSYS A/D Clock Period (tADCK) SACKS [2:0]=000 (fSYS) SACKS [2:0]=001 (fSYS/2) SACKS [2:0]=010 (fSYS/4) SACKS [2:0]=011 (fSYS/8) SACKS [2:0]=100 (fSYS/16) SACKS [2:0]=101 (fSYS/32) SACKS [2:0]=110 (fSYS/64) SACKS [2:0]=111 (fSYS/128) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * �MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4MHz �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8MHz 1�5ns * �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 1�MHz 83ns * 1�7ns * 333ns * ��7ns 1.33μs 2.67μs 5.33μs 10.67μs* A/D Clock Period Examples Controllingthepoweron/offfunctionoftheA/Dconvertercircuitryisimplementedusingthe ADCENbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.When theADCENbitissethightopowerontheA/Dconverterinternalcircuitryacertaindelay,as indicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.Evenif nopinsareselectedforuseasA/Dinputs,iftheADCENbitishigh,thensomepowerwillstillbe consumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADCENissetlow toreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused. |
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