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数据搜索系统，热门电子元器件搜索 |
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HT66F4530 数据表(PDF) 136 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 136 Page - Holtek Semiconductor Inc |
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136 / 224 page  Rev. 1.00 13� De�e��e� �1� �01� Rev. 1.00 137 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers SPI Communication AftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,when dataiswrittentotheSIMDregister,transmission/receptionwillbeginsimultaneously.Whenthe datatransferiscomplete,theTRFflagwillbesetautomatically,butmustbeclearedusingthe applicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived, anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedinto theSIMDregister.ThemastershouldoutputanSCSsignaltoenabletheslavedevicesbeforea clocksignalisprovided.Theslavedatatobetransferredshouldbewellpreparedattheappropriate momentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEG bit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignal forvariousconfigurationsoftheCKPOLBandCKEGbits. TheSPIwillcontinuetofunctioninspecialIDLEModesiftheclocksourceusedbytheSPI interfaceisstillactive. SCK (CKPOLB=1� CKEG=0) SCK (CKPOLB=0� CKEG=0) SCK (CKPOLB=1� CKEG=1) SCK (CKPOLB=0� CKEG=1) SCS SDO (CKEG=0) SDO (CKEG=1) SDI Data Captu�e W�ite to SIMD SIMEN� CSEN=1 SIMEN=1� CSEN=0 (Exte�nal Pull-high) D7/D0 D�/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D� D0/D7 D7/D0 D�/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D� D0/D7 SPI Master Mode Timing SCK (CKPOLB=1) SCK (CKPOLB=0) SCS SDO SDI Data Captu�e W�ite to SIMD (SDO does not �hange until fi�st SCK edge) D7/D0 D�/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D� D0/D7 SPI Slave Mode Timing – CKEG=0 |
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