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数据搜索系统，热门电子元器件搜索 |
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HT66F4530 数据表(PDF) 138 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 138 Page - Holtek Semiconductor Inc |
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138 / 224 page  Rev. 1.00 138 De�e��e� �1� �01� Rev. 1.00 139 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers SPI Bus Enable/Disable ToenabletheSPIbus,setCSEN=1andSCS=0,thenwaitfordatatobewrittenintotheSIMD (TXRXbuffer)register.FortheMasterMode,afterdatahasbeenwrittentotheSIMD(TXRX buffer)register,thentransmissionorreceptionwillstartautomatically.Whenallthedatahasbeen transferred,theTRFbitshouldbesethigh.FortheSlaveMode,whenclockpulsesarereceivedon SCK,dataintheTXRXbufferwillbeshiftedoutordataonSDIwillbeshiftedin. WhentheSPIbusisdisabled,SCK,SDI,SDOandSCScanbecomeI/Opinsorotherpin-shared functionsusingthecorrespondingpin-sharedcontrolbits. SPI Operation Allcommunicationiscarriedoutusingthe4-lineinterfaceforeitherMasterorSlaveMode. TheCSENbitintheSIMC2registercontrolstheoverallfunctionoftheSPIinterface.Settingthis bithighwillenabletheSPIinterfacebyallowingtheSCSlinetobeactive,whichcanthenbeused tocontroltheSPIinterface.IftheCSENbitislow,theSPIinterfacewillbedisabledandtheSCS linewillbeinafloatingconditionandcanthereforenotbeusedforcontroloftheSPIinterface. IftheCSENbitandtheSIMENbitintheSIMC0aresethigh,thiswillplacetheSDIlineina floatingconditionandtheSDOlinehigh.IfinMasterModetheSCKlinewillbeeitherhighorlow dependingupontheclockpolarityselectionbitCKPOLBintheSIMC2register.IfinSlaveMode theSCKlinewillbeinafloatingcondition.IftheSIMENbitislow,thenthebuswillbedisabled andSCS,SDI,SDOandSCKwillallbecomeI/Opinsortheotherfunctionsusingthecorresponding pin-sharedcontrolbits.IntheMasterModetheMasterwillalwaysgeneratetheclocksignal.The clockanddatatransmissionwillbeinitiatedafterdatahasbeenwrittenintotheSIMDregister. IntheSlaveMode,theclocksignalwillbereceivedfromanexternalmasterdeviceforbothdata transmissionandreception.Thefollowingsequencesshowtheordertobefollowedfordatatransfer inbothMasterandSlaveMode. • Master Mode: • Step1 SelecttheSPIMastermodeandclocksourceusingtheSIM2~SIM0bitsintheSIMC0control register. • Step2 SetuptheCSENbitandsetuptheMLSbittochooseifthedataisMSBorLSBfirst,thissetting mustbethesamewiththeSlavedevices. • Step3 SetuptheSIMENbitintheSIMC0controlregistertoenabletheSPIinterface. • Step4 Forwriteoperations:writethedatatotheSIMDregister,whichwillactuallyplacethedatainto theTXRXbuffer.ThenusetheSCKandSCSlinestooutputthedata.Afterthis,gotostep5. Forreadoperations:thedatatransferredinontheSDIlinewillbestoredintheTXRXbuffer untilallthedatahasbeenreceivedatwhichpointitwillbelatchedintotheSIMDregister. • Step5 ChecktheWCOLbitifsethighthenacollisionerrorhasoccurredsoreturntostep4.Ifequalto zerothengotothefollowingstep. • Step6 ChecktheTRFbitorwaitforaSPIserialbusinterrupt. • Step7 ReaddatafromtheSIMDregister. |
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