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RT5021 数据表(PDF) 35 Page - Richtek Technology Corporation |
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RT5021 数据表(HTML) 35 Page - Richtek Technology Corporation |
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35 / 67 page ![]() RT5021 35 DS5021-01 April 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. © During On sequence period, EN going low would not take effect. After the sequence finish, EN state would be re-checked and decide to keep on or start off sequence. During Off sequence period, EN going high would not take effect. After the sequence finish, EN state would be re-checked and decide to keep off or start on sequence. External EN VOUT3 (1.1V) SEQ_Ready VREF/IREF /OSC/POR VOUT4 (1.5V) Latch SEQ detection result tR 4ms tD 10ms tD 10ms VOUT1 (5V) tR 4ms VOUT6 Enabled in I 2 C VOUT2 (3.3V) VOUT5 Each Enabled in I 2 C ≈ ≈ ≈ ≈ tR 4ms ≈ tD 10ms ≈ External EN VOUT3 (1.1V) SEQ_Ready VREF/IREF/ OSC/POR VOUT4 (1.5V) Latch SEQ detection result tR 4ms tD 10ms tD 10ms VOUT1 (5V) tR 4ms VOUT2 (3.3V) Last channel discharge finish and then reset SEQ detection result and issue next time to re-detect SEQ Latch SEQ detection result EN going low take no effect during on sequence period. ≈ ≈ ≈ ≈ tR 4ms ≈ tD 10ms ≈ tR 4ms ≈ tD 10ms ≈ tR 4ms ≈ tD 10ms ≈ tR 4ms ≈ tD 10ms ≈ |
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