RT5021 datasheet(17/67 Pages) RICHTEK

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RT5021

DS5021-01 April 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Note 1. Stresses beyond those listed

“Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2.

θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

SDA, SCLK Input High Level

Threshold

1.4

SDA, SCLK Input Low Level

Threshold

0.6

SCLK Clock Rate

fSCL

400

kHz

Hold Time (repeated) START

Condition.

After this period, the first clock

pulse is generated.

tHD,STA

0.6

μs

LOW Period of the SCL Clock

tLOW

1.3

μs

HIGH Period of the SCL Clock

tHIGH

0.6

μs

Set-Up Time for a Repeated

START Condition

tSU,STA

0.6

μs

Data Hold Time

tHD,DAT

0.9

μs

Data Set-Up Time

tSU,DAT

100

Set-Up Time for STOP

Condition

tSU,STO

0.6

μs

Bus Free Time between a

STOP and START condition

tBUF

1.3

μs

Rise time of both SDA and

SCL signals

300

Fall Time of Both SDA and

SCL Signals

300

SDA and SCL Output Low Sink

Current

IOL

SDA or SCL voltage = 0.4V

(VSYS = 3.3V, TA = 25

°C, unless otherwise specified)

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