RT5021 datasheet(63/67 Pages) RICHTEK

63 / 67 page

RT5021

DS5021-01 April 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WQFN-40L 5x5 package, the thermal resistance,

θJA, is

27.5

°C/W on a standard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at TA = 25

°C

can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (27.5°C/W) = 3.64W for

WQFN-40L 5x5 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 6 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Layout Consideration

For the best performance of the RT5021, the following

PCB layout guidelines must be strictly followed.

Place the input and output capacitors as close as

possible to the input and output pins respectively for

good filtering.

Keep the main power traces as wide and short as

possible.

The switching node area connected to LX and inductor

should be minimized for lower EMI.

Place the feedback components as close as possible

to the FB pin and keep these components away from

the noisy devices.

Connect the GND and Exposed Pad to a strong ground

plane for maximum thermal dissipation and noise

protection.

To make CH1 and whole chip stable, the power path

from the PVD1 pin to its output capacitors must be as

short (

≤ 1mm is better) and wide as possible.

To make CH4 and CH5 stable, the power path from the

PVD45 pin to its input capacitors must be as short (

≤

1mm is better) and wide as possible.

Figure 6. Derating Curve of Maximum Power Dissipation

0.0

0.8

1.6

2.4

3.2

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

RT5021 数据表(PDF) 63 Page - Richtek Technology Corporation

RT5021 数据表(HTML) 63 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载