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RT5021 数据表(PDF) 64 Page - Richtek Technology Corporation |
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RT5021 数据表(HTML) 64 Page - Richtek Technology Corporation |
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64 / 67 page ![]() RT5021 64 DS5021-01 April 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. © Figure 7. PCB Layout Guide L1 R16 L3 D5 D4 C19 L7 L2 R7 C10 C12 L4 C23 L5 D2 VOUT_CH1 VOUT_CH4 VOUT_CH3 VOUT_CH2 VSYS GND GND VOUT_CH7 GND LX should be connected to Inductor by wide and short trace, and keep sensitive components away from this trace. Connect the Exposed Pad to a ground plane. Place the feedback components as close as possible to the FB pin and keep away from noisy devices. Input/Output capacitors must be placed as close as possible to the Input/Output pins. C4 VOUT_CH6 D3 C21 C3 VSYS C22 C11 R8 D6 D7 VSYS GND C24 GND VOUT_CH8 GND GND GND C18 R4 R3 C7 C6 C5 R1 R2 RNTC R6 R5 C9 C8 C2 C1 C14 C25 C26 C17 WAKE LX1 PVD6 VO6 LX7 FB7 PVD7 PVD1 VP PVD2 FB3 SCL VO8 FB2 VO2 LX2A LX2B TS 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 GND CHG2 CHG C27 C28 Output capacitor must be placed as close as possible to the output pin. |
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