RT5021 datasheet(37/67 Pages) RICHTEK

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RT5021

DS5021-01 April 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

INT vs. Fault/Status Timing Diagram

Interrupt vs. Events (I2C Status Bits)

When PMU turns on with event

condition

During PMU on

INT assert

(Turn to low)

No Event (0)

Event has

occurred (1)

Event appear

→ 1)

Event disappear

→ 0)

PGOOD

Yes

NoBAT

Yes

TS_METER [2:0] = 000

(Event may be cold or

hot, VP UVLO, NoBAT)

Yes

EOC

Yes

THR

Yes

SAFE

Yes

DPM

Yes

CHGRUN

Yes

THR

EOC

PGOOD

A9.INT bit is written to "0"

TS_Meter [2:0]

NoBAT

CHGRUN

DPM

SAFE

INT

When the A9.INT bit is written to "0", the INT will be set to high.

When Mask_DPM = 1 and DPM event change, the INT would not be asserted.

(Mask_DPM = 0)

Interrupt Indicator

The RT5021 provides an interrupt indicator output pin (INT). INT is an open drain output which is controlled by A9.INT bit.

When the PGOOD, TS_Meter [2:0], EOC, THR, SAFE, NoBAT, CHGRUN, DPM status bits toggle, the A9.INT bit will be

set to high. In order to reset the interrupt status, a

“0” must be written to the A9.INT bit or power on the PMU again. The

timing diagram is shown below :

RT5021 数据表(PDF) 37 Page - Richtek Technology Corporation

RT5021 数据表(HTML) 37 Page - Richtek Technology Corporation

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