WM8971LEFLSLASHR datasheet(44/56 Pages) WOLFSON

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WM8971L

Advanced Information

AI Rev 3.0 March 2004

POWER MANAGEMENT

The WM8971L has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,

it is important to enable or disable functions in the correct order (see Applications Information).

VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a

50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled,

as a 500kOhm potential divider.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

Vmid divider enable and select

00 – Vmid disabled (for OFF mode)

01 – 50kOhm divider enabled (for

playback/record)

10 – 500kOhm divider enabled (for low-power

standby)

11 – 5kOhm divider enabled (for fast start-up)

VREF

VREF (necessary for all other functions)

AINL

Analogue in PGA Left

AINR

Analogue in PGA Right

ADCL

ADC Left

ADCR

ADC Right

R25 (19h)

Power

Management

(1)

MICB

MICBIAS

DACL

DAC Left

DACR

DAC Right

LOUT1

LOUT1 Output Buffer*

ROUT1

ROUT1 Output Buffer*

LOUT2

LOUT2 Output Buffer*

ROUT2

ROUT2 Output Buffer*

R26 (1Ah)

Power

Management

(2)

MONO

MONOOUT Output Buffer and Mono Mixer

Note: All control bits are 0=OFF, 1=ON

* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when

ROUT1=1 or ROUT2=1.

Table 36 Power Management

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8971L, the master clock should be

stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode with all supplies at 3.3V, setting DIGENB saves approximately 0.27mA on DCVDD

and 0.2mA on DBVDD. However, since setting DIGENB has no effect on the power consumption of

other system components external to the WM8971L, it is preferable to disable the master clock at its

source wherever possible.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 37 ADC and DAC Oversampling Rate Selection

NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set to

zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent

DACs and ADCs from re-starting correctly.

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