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WM8971LEFL/R 数据表(PDF) 21 Page - Wolfson Microelectronics plc |
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WM8971LEFL/R 数据表(HTML) 21 Page - Wolfson Microelectronics plc |
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21 / 56 page ![]() Advanced Information WM8971L w AI Rev 3.0 March 2004 21 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8971L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0 Volts r.m.s. Any voltage greater than full scale may overload the ADC and cause distortion. ADC DIGITAL FILTER The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in Figure 7. FROM ADC DIGITAL HPF DIGITAL FILTER TO DIGITAL AUDIO INTERFACE DIGITAL DECIMATOR ADCHPD Figure 7 ADC Digital Filter The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the DC offset is changed, the stored and subtracted value will not change unless the high-pass filter is enabled. This feature can be used for calibration purposes. The output data format can be programmed by the user to accommodate stereo or monophonic recording on both inputs. The polarity of the output signal can also be changed under software control. The software control is shown in Table 7. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:5 ADCPOL [1:0] 00 00 = Polarity not inverted 01 = L polarity invert 10 = R polarity invert 11 = L and R polarity invert 4 HPOR 0 Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset R5 (05h) ADC and DAC Control 0 ADCHPD 0 ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter Table 7 ADC Signal Path Control |
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