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WM8971LEFL/R 数据表(PDF) 46 Page - Wolfson Microelectronics plc |
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WM8971LEFL/R 数据表(HTML) 46 Page - Wolfson Microelectronics plc |
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46 / 56 page ![]() WM8971L Advanced Information w AI Rev 3.0 March 2004 46 REGISTER MAP REGISTER ADDRESS (Bit 15 – 9) remarks Bit[8] Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] default page ref R0 (00h) 0000000 Left Input volume LIVU LINMUTE LIZC LINVOL 010010111 20 R1 (01h) 0000001 Right Input volume RIVU RINMUTE RIZC RINVOL 010010111 20 R2 (02h) 0000010 LOUT1 volume LO1VU LO1ZC LOUT1VOL[6:0] 001111001 31 R3 (03h) 0000011 ROUT1 volume RO1VU RO1ZC ROUT1VOL[6:0] 001111001 31 R4 (04h) 0000100 Reserved 0 0 0 0 0 0 0 0 0 000000000 - R5 (05h) 0000101 ADC and DAC Control ADCDIV2 DACDIV2 ADCPOL[1:0] HPOR DACMU DEEMPH[1:0] ADCHPD 000001000 20,25,28 R6 (06h) 0000110 Reserved 0 0 0 0 0 0 0 0 0 000000000 - R7 (07h) 0000111 Audio Interface 0 BCLKINV MS LRSWAP LRP WL[1:0] FORMAT[1:0] 000001010 39 R8 (08h) 0001000 Sample rate 0 0 CLKDIV2 SR[4:0] USB 000000000 40 R9 (09h) 0001001 Reserved 0 0 0 0 0 0 0 0 0 000000000 - R10 (0Ah) 0001010 Left DAC volume LDVU LDACVOL[7:0] 011111111 26 R11 (0Bh) 0001011 Right DAC volume RDVU RDACVOL[7:0] 011111111 26 R12 (0Ch) 0001100 Bass control 0 BB BC 0 0 BASS[3:0] 000001111 27 R13 (0Dh) 0001101 Treble control 0 0 TC 0 0 TRBL[3:0] 000001111 27 R15 (0Fh) 0001111 Reset writing to this register resets all registers to their default state not reset - R16 (10h) 0010000 Reserved 0 0 0 0 0 0 0 0 0 000000000 - R17 (11h) 0010001 ALC1 ALCSEL[1:0] MAXGAIN[2:0] ALCL[3:0] 001111011 24 R18 (12h) 0010010 ALC2 0 ALCZC 0 0 0 HLD[3:0] 000000000 24 R19 (13h) 0010011 ALC3 0 DCY[3:0] ATK[3:0] 000110010 24 R20 (14h) 0010100 Noise Gate 0 NGTH[4:0] NGG[1:0] NGAT 000000000 25 R21 (15h) 0010101 Left ADC volume LAVU LADCVOL[7:0] 011000011 22 R22 (16h) 0010110 Right ADC volume RAVU RADCVOL[7:0] 011000011 22 R23 (17h) 0010111 Additional control(1) TSDEN VSEL[1:0] DMONOMIX[1:0] DATSEL[1:0] DACINV TOEN 011000000 18,20,28,35 R24 (18h) 0011000 Additional control(2) 0 0 HPSWEN HPSWPOL ROUT2INV TRI LRCM ADCOSR DACOSR 000000000 32, 34,46 R25 (19h) 0011001 Pwr Mgmt (1) VMIDSEL[1:0] VREF AINL AINR ADCL ADCR MICB DIGENB 000000000 44 R26 (1Ah) 0011010 Pwr Mgmt (2) DACL DACR LOUT1 ROUT1 LOUT2 ROUT2 MONO 0 0 000000000 44 R27 (1Bh) 0011011 Additional Control (3) ADCLRM[1:0] VROI 0 0 0 0 0 0 000000000 35 R31 (1Fh) 0011111 ADC input mode DS MONOMIX[1:0] 0 0 0 0 0 0 000000000 18 R32 (20h) 0100000 ADCL signal path 0 LINSEL[1:0] LMICBOOST[1:0] 0 0 0 0 000000000 18 R33 (21h) 0100001 ADCR signal path 0 RINSEL[1:0] RMICBOOST[1:0] 0 0 0 0 000000000 18 R34 (22h) 0100010 Left out Mix (1) LD2LO LI2LO LI2LOVOL[2:0] 0 LMIXSEL[2:0] 001010000 29 R35 (23h) 0100011 Left out Mix (2) RD2LO RI2LO RI2LOVOL[2:0] 0 0 0 0 001010000 29 R36 (24h) 0100100 Right out Mix (1) LD2RO LI2RO LI2ROVOL[2:0] 0 RMIXSEL[2:0] 001010000 30 R37 (25h) 0100101 Right out Mix (2) RD2RO RI2RO RI2ROVOL[2:0] 0 0 0 0 001010000 30 R38 (26h) 0100110 Mono out Mix (1) LD2MO LI2MO LI2MOVOL[2:0] 0 0 0 0 001010000 30 R39 (27h) 0100111 Mono out Mix (2) RD2MO RI2MO RI2MOVOL[2:0] 0 0 0 0 001010000 30 R40 (28h) 0101000 LOUT2 volume LO2VU LO2ZC LOUT2VOL[6:0] 001111001 32 R41 (29h) 0101001 ROUT2 volume RO2VU RO2ZC ROUT2VOL[6:0] 001111001 32 R42 (2Ah) 0101010 MONOOUT volume 0 MOZC MOUTVOL[6:0] 001111001 32 Note: 1. All unused register bits must be set to ‘0’ when writing to WM8971L. |
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