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WM8971LEFL/R 数据表(PDF) 36 Page - Wolfson Microelectronics plc

部件名 WM8971LEFL/R
功能描述  STEREO CODEC FOR PORTABLE AUDIO APPLLICATIONS
PDF  56 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8971LEFL/R 数据表(HTML) 36 Page - Wolfson Microelectronics plc

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WM8971L
Advanced Information
w
AI Rev 3.0 March 2004
36
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
fc. Assuming a 10 kOhm load and C1, C2 = 1
µF:
fc = 1 / 2
π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz
Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8971L and outputting ADC data
from it. It uses five pins:
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
ADCLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8971L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
Left justified
Right justified
I
2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8971L can be configured as either a master or slave mode device. As a master device the
WM8971L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8971L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.
Figure 14 Master Mode
Figure 15 Slave Mode



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