WM8971LEFLSLASHR datasheet(37/56 Pages) WOLFSON

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WM8971L

AI Rev 3.0 March 2004

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 16 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 17 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 18 I

2S Justified Audio Interface (assuming n-bit word length)

WM8971LEFL/R 数据表(PDF) 37 Page - Wolfson Microelectronics plc

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WM8971LEFL/R 数据表(PDF) 37 Page - Wolfson Microelectronics plc

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