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WM8972LEFL/R 数据表(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8972LEFL/R 数据表(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 49 page  Preliminary Technical Data WM8972L w PTD Rev 2.2 June 2004 11 CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SCLK to SDIN hold time tDHO 40 ns CSB pulse width low tCSL 40 ns CSB pulse width high tCSH 40 ns CSB rising to SCLK rising tCSS 40 ns Pulse width of spikes that will be suppressed tps 5 ns |
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