WM8972LEFLSLASHR datasheet(15/49 Pages) WOLFSON

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Preliminary Technical Data

WM8972L

PTD Rev 2.2 June 2004

PGA CONTROL

The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically

adjustable from +30dB to –17.25dB in 0.75dB steps. The PGA can be controlled either by the user or

by the ALC function (see Automatic Level Control). When ALC is enabled then writing to the PGA

control register has no effect.

Setting the ZCEN bit enables a zero-cross detector which ensures that PGA gain changes only occur

when the signal is at zero, eliminating any zipper noise. If zero cross is enabled a timeout is also

available to update the gain if a zero cross does not occur. This function may be enabled by setting

TOEN in register R23 (17h).

The inputs can also be muted in the analogue domain under software control. The software control

registers are shown in Table 5. If zero crossing is enabled, it is necessary to enable zero cross

timeout to un-mute the input PGAs. This is because their outputs will not cross zero when muted.

Alternatively, zero cross can be disables before sending the un-mute command.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IVU

Volume Update

0 = Store INVOL in intermediate

latch (no gain change)

1 = Update gains

INMUTE

Analogue Mute

1 = Enable Mute

0 = Disable Mute

Note: IVU must be set to un-mute.

ZCEN

Zero Cross Detector

1 = Change gain on zero cross only

0 = Change gain immediately

R0 (00h)

PGA

5:0

INVOL

[5:0]

010111

( 0dB )

Input Volume Control

111111 = +30dB

111110 = +29.25dB

. . 0.75dB steps down to

000000 = -17.25dB

R23 (17h)

Additional

Control (1)

TOEN

Timeout Enable

0 : Timeout Disabled

1 : Timeout Enabled

Table 5 Input PGA Software Control

WM8972LEFL/R 数据表(PDF) 15 Page - Wolfson Microelectronics plc

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