WM8972LEFLSLASHR datasheet(19/49 Pages) WOLFSON

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Preliminary Technical Data

WM8972L

PTD Rev 2.2 June 2004

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ALCSEL

(OFF)

ALC function select

0 = ALC off (PGA gain set by register)

1 = ALC on

6:4

MAXGAIN

[2:0]

111

(+30dB)

Set Maximum Gain of PGA

111 : +30dB

110 : +24dB

….(-6dB steps)

001 : -6dB

000 : -12dB

R17 (11h)

ALC Control 1

3:0

ALCL

[3:0]

1011

(-12dB)

ALC target – sets signal level at ADC

input

0000 = -28.5dB FS

0001 = -27.0dB FS

… (1.5dB steps)

1110 = -7.5dB FS

1111 = -6dB FS

ALCZC

0 (zero

cross

off)

ALC uses zero cross detection circuit.

R18 (12h)

ALC Control 2

3:0

HLD

[3:0]

0000

(0ms)

ALC hold time before gain is increased.

0000 = 0ms

0001 = 2.67ms

0010 = 5.33ms

… (time doubles with every step)

1111 = 43.691s

7:4

DCY

[3:0]

0011

(192ms)

ALC decay (gain ramp-up) time

0000 = 24ms

0001 = 48ms

0010 = 96ms

… (time doubles with every step)

1010 or higher = 24.58s

R19 (13h)

ALC Control 3

3:0

ATK

[3:0]

0010

(24ms)

ALC attack (gain ramp-down) time

0000 = 6ms

0001 = 12ms

0010 = 24ms

… (time doubles with every step)

1010 or higher = 6.14s

Table 8 ALC Control

PEAK LIMITER

To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a

limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is

ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below

87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.

Note:

If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to

prevent clipping when long attack times are used.

WM8972LEFL/R 数据表(PDF) 19 Page - Wolfson Microelectronics plc

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WM8972LEFL/R 数据表(PDF) 19 Page - Wolfson Microelectronics plc

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