WM8972LEFLSLASHR datasheet(36/49 Pages) WOLFSON

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WM8972L

Preliminary Technical Data

PTD Rev 2.2 June 2004

POWER MANAGEMENT

The WM8972L has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,

it is important to enable or disable functions in the correct order (see Applications Information).

VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a

50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled,

as a 500kOhm potential divider.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

Vmid divider enable and select

00 – Vmid disabled (for OFF mode)

01 – 50kOhm divider enabled (for

playback/record)

10 – 500kOhm divider enabled (for low-power

standby)

11 – 5kOhm divider enabled (for fast start-up)

VREF

VREF (necessary for all other functions)

AIN

Analogue in PGA

ADC

R25 (19h)

Power

Manageme

nt (1)

MICB

MICBIAS

DAC

OUT+

OUT+ Output Buffer*

OUT-

OUT- Output Buffer*

MONO

MONOOUT Output Buffer and Mono Mixer

R26 (1Ah)

Power

Manageme

nt (2)

OUT2

OUT2 Output Buffer

Note: All control bits are 0=OFF, 1=ON

* The plus mixer is enabled when OUT+=1. The minus mixer is enabled when OUT-=1.

Table 32 Power Management

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8972L, the master clock should be

stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode with all supplies at 3.3V, setting DIGENB saves approximately 0.27mA on DCVDD

and 0.2mA on DBVDD. However, since setting DIGENB has no effect on the power consumption of

other system components external to the WM8972L, it is preferable to disable the master clock at its

source wherever possible.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 33 ADC and DAC Oversampling Rate Selection

NOTE: Before DIGENB can be set, the control bits ADC, DAC must be set to zero and a waiting

time of 1ms must be observed. Any failure to follow this procedure may prevent the DAC and

ADC from re-starting correctly.

WM8972LEFL/R 数据表(PDF) 36 Page - Wolfson Microelectronics plc

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