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AD9268 数据表(PDF) 39 Page - Analog Devices |
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AD9268 数据表(HTML) 39 Page - Analog Devices |
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39 / 45 page ![]() AD9268 Rev. A | Page 38 of 44 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Address (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments Chip Configuration Registers 0x00 SPI port configuration (global) 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles are mirrored so LSB-first mode or MSB- first mode registers correctly, regardless of shift mode 0x01 Chip ID (global) 8-bit Chip ID[7:0] (AD9268 = 0x32) (default) 0x32 Read only 0x02 Chip grade (global) Open Open Speed grade ID 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS Open Open Open Open Speed grade ID used to differentiate devices; read only Channel Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open Data Channel B (default) Data Channel A (default) 0x03 Bits are set to determine which device on the chip receives the next write command; applies to local registers only 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Functions 0x08 Power modes (local) 1 Open External power- down pin function (local) 0 = pdwn 1 = stndby Open Open Open Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation 0x80 Determines various generic modes of chip operation 0x09 Global clock (global) Open Open Open Open Open Open Open Duty cycle stabilizer (default) 0x01 0x0B Clock divide (global) Open Open Open Open Open Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active 0x0D Test mode (local) Open Open Reset PN long gen Reset PN short gen Open Output test mode 000 = off (default) 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle 0x00 When this register is set, the test data is placed on the output pins in place of normal data |
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