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AD9268 数据表(PDF) 1 Page - Analog Devices |
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AD9268 数据表(HTML) 1 Page - Analog Devices |
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1 / 45 page  16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9268 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. FEATURES SNR = 78.2 dBFS @ 70 MHz and 125 MSPS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS Optional on-chip dither Programmable internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM CMOS/LVDS OUTPUT BUFFER CMOS/LVDS OUTPUT BUFFER ADC DRVDD CSB AVDD SPI SDIO/ DCS SCLK/ DFS PROGRAMMING DATA DUTY CYCLE STABILIZER DIVIDE 1 TO 8 DCO GENERATION REF SELECT MULTICHIP SYNC SYNC AGND NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. PDWN OEB DCOB DCOA D15A (MSB) TO D0A (LSB) D15B (MSB) TO D0B (LSB) ORA CLK– CLK+ ORB VIN+A VCM RBIAS VIN–B VIN+B VIN–A VREF SENSE AD9268 ADC 16 16 Figure 1. PRODUCT HIGHLIGHTS 1. On-chip dither option for improved SFDR performance with low power analog input. 2. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. 3. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. 4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 5. Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications. |
类似零件编号 - AD9268 |
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类似说明 - AD9268 |
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