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AD9268 数据表(PDF) 31 Page - Analog Devices |
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AD9268 数据表(HTML) 31 Page - Analog Devices |
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31 / 45 page  AD9268 Rev. A | Page 30 of 44 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 62). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. 0.5 1.0 1.5 2.0 0 –0.5 –1.0 –1.5 –2.0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) VREF = 1.0V Figure 73. Typical VREF Drift CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9268 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 74) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. AVDD CLK+ 4pF 4pF CLK– 0.9V Figure 74. Equivalent Clock Input Circuit Clock Input Options The AD9268 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 75 and Figure 76 show two preferred methods for clocking the AD9268 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- mended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9268 to approx- imately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9268 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 0.1µF 0.1µF 0.1µF 0.1µF SCHOTTKY DIODES: HSMS2822 CLOCK INPUT 50 Ω 100 Ω CLK– CLK+ ADC AD9268 Mini-Circuits® ADT1-1WT, 1:1Z XFMR Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz) 0.1µF 0.1µF 1nF CLOCK INPUT 1nF 50 Ω CLK– CLK+ SCHOTTKY DIODES: HSMS2822 ADC AD9268 Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz) If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers offer excellent jitter performance. 100 Ω 0.1µF 0.1µF 0.1µF 0.1µF 240 Ω 240 Ω PECL DRIVER 50k Ω 50k Ω CLK– CLK+ CLOCK INPUT CLOCK INPUT AD951x ADC AD9268 Figure 77. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518 clock drivers offer excellent jitter performance. 100 Ω 0.1µF 0.1µF 0.1µF 0.1µF 50k Ω 50k Ω CLK– CLK+ CLOCK INPUT CLOCK INPUT AD951x LVDS DRIVER ADC AD9268 Figure 78. Differential LVDS Sample Clock (Up to 625 MHz) |
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