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AD9268

Rev. A | Page 16 of 44

Pin No.

Mnemonic

Type

Description

D3−

Output

Channel A/Channel B LVDS Output Data 3—Complement.

D4+

Output

Channel A/Channel B LVDS Output Data 4—True.

D4−

Output

Channel A/Channel B LVDS Output Data 4—Complement.

D5+

Output

Channel A/Channel B LVDS Output Data 5—True.

D5−

Output

Channel A/Channel B LVDS Output Data 5—Complement.

D6+

Output

Channel A/Channel B LVDS Output Data 6—True.

D6−

Output

Channel A/Channel B LVDS Output Data 6—Complement.

D7+

Output

Channel A/Channel B LVDS Output Data 7—True.

D7−

Output

Channel A/Channel B LVDS Output Data 7—Complement.

D8+

Output

Channel A/Channel B LVDS Output Data 8—True.

D8−

Output

Channel A/Channel B LVDS Output Data 8—Complement.

D9+

Output

Channel A/Channel B LVDS Output Data 9—True.

D9−

Output

Channel A/Channel B LVDS Output Data 9—Complement.

D10+

Output

Channel A/Channel B LVDS Output Data 10—True.

D10−

Output

Channel A/Channel B LVDS Output Data 10—Complement.

D11+

Output

Channel A/Channel B LVDS Output Data 11—True.

D11−

Output

Channel A/Channel B LVDS Output Data 11—Complement.

D12+

Output

Channel A/Channel B LVDS Output Data 12—True.

D12−

Output

Channel A/Channel B LVDS Output Data 12—Complement.

D13+

Output

Channel A/Channel B LVDS Output Data 13—True.

D13−

Output

Channel A/Channel B LVDS Output Data 13—Complement.

D14+

Output

Channel A/Channel B LVDS Output Data 14—True.

D14−

Output

Channel A/Channel B LVDS Output Data 14—Complement.

D15+ (MSB)

Output

Channel A/Channel B LVDS Output Data 15—True.

D15− (MSB)

Output

Channel A/Channel B LVDS Output Data 15—Complement.

OR+

Output

Channel A/Channel B LVDS Overrange Output—True.

OR−

Output

Channel A/Channel B LVDS Overrange Output—Complement.

DCO+

Output

Channel A/Channel B LVDS Data Clock Output—True.

DCO−

Output

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

SCLK/DFS

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

SDIO/DCS

Input/Output

SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.

CSB

Input

SPI Chip Select (Active Low).

ADC Configuration

OEB

Input

Output Enable Input (Active Low) in External Pin Mode.

PDWN

Input

Power-Down Input in External Pin Mode. In SPI mode, this input can be

configured as power-down or standby.

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