L9679P datasheet(166/272 Pages) STMICROELECTRONICS

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Deployment drivers

L9679P

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DocID029275 Rev 1

During TFETTIMEOUT period, the bit stating that the FET is enabled will be set (FETON=1)

and will be cleared as soon as the FET is switched back off.

For all conditions the current on SFx/SRx pins will not exceed the VRCM current limitation

value (ILIM_VRCM_SINK or ILIM_VRCM_SRC). There may be higher currents on the squib lines

due to the presence of filter capacitors. During these FET tests, energy available to the

squib is limited to less than EFET_TEST. For high side FET diagnostics, if no faults were

indicated in the preceding leakage diagnostics then a normal result would be [STB=1,

STG=0]. If the returned result for the high side FET test is not as the previous then either the

FET is not functional, a short to ground occurred during the test, or there is a missing SSxy

connection for that channel.

For low side FET diagnostics if no faults were indicated in the preceding leakage

diagnostics then a normal result would be [STB=0, STG=1]. If the returned result for the low

side FET test is not as the previous then either the FET is not functional or a short to battery

occurred during the test. In case of ground loss the low-side FET diagnostic would not

indicate a FET fault.

The VRCM flags will be given in the LPDIAGSTAT register. The status of the VRCM flags

after FET test is latched and can be cleared upon either LPDIAGREQ or SYSDIAGREQ SPI

commands.

Finally, after FET test is completed, the VRCM deglitch filter time is switched from the FET

test deglitch filter time (TFLT_LKGB_FT) to the leakage diagnostic test deglitch filter time

Table 11. HS FET TEST

VRCM Flags

Result

STG

STB

FET test fail

FET test pass

Leakage to Vbat

FET test disabled

due to Leakage to Gd

State not possible

Table 12. LS FET TEST

VRCM Flags

Result

STG

STB

FET test fail

FET test disabled

due to Leakage to Vbat

FET test pass

Leakage to GND

State not possible

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