L9679P datasheet(167/272 Pages) STMICROELECTRONICS

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L9679P

Deployment drivers

271

(TFLT_LKG) for both HS and LS and the output of the VRCM deglitch filter is now not

allowed to disable the appropriate HS or LS squib driver anymore.

High side driver diagnostics

This test is intended to verify the proper functionality of the HS FET driver, but also the

external squib connection and other internal circuitries.

First, the ISNK current has to be activated via the LPDIAGREQ register; the channel onto

which the ISNK current is activated has to be selected with the RES_MEAS_CHSEL bit

field. Then, the HS FET related to the loop channel as indicated in the RES_MEAS_CHSEL

bit field is activated with the dedicated DSTEST code for the HS squib driver test in the

Diagnostic Register SPI command (SYSDIAGREQ). In such condition, the HS driver will

control the FET current to a level ILIM_HS_FET much lower than the usual deployment

current. The HS_DRV_OK flag will be set accordingly to the test result in the LPDIAGSTAT

current through the HS FET exceeds the diagnostic current threshold, 90%*ILIM_HS_FET.

Loss of ground return diagnostics

This diagnostics is available during a squib measurement or a high side driver diagnostics.

This test is based on the voltage drop across the ground return, if the voltage drop exceeds

SGxy_OPEN, ground connection is considered as lost. Should the ground connection on the

squib driver circuit be missing, the bit related to the channel under test by the two above

diagnostics will be activated in the LP_GNDLOSS register. The flag is latched after a proper

filter time TFLT_SGOPEN and cleared upon read.

High side safing FET diagnostics

This test has to be issued during the Diag state of the power-up sequence (Figure 10).

Safing FET has to be switched on with the proper code in DSTEST bit field of the

SYSDIAGREQ. Therefore, when the command is received, the device will activate VSF

regulator to supply the external safing FET controller. The user can measure the voltage

levels of both the VSF regulator and the SSxy nodes. If the safing FET is properly switched

on, the voltage on SSxy will be regulated.

The measurement request is done via Diagnostic Control command (DIAGCTRLx), while

results will be reported through ADCRESx bit fields.

Deployment Timer diagnostic

This test allows verifying the correct functionality and duration of the timers used to control

the deployment times. This test can be executed only when the IC is in the Diag state by

setting the appropriate code in the DSTEST field of the SYSDIAGREQ register. When the

test is launched, the IC sequentially triggers the activation of the deployment timers of the

various channels (each of them separated by 8ms idle time) and outputs the relevant

waveform to the ARM1 output discrete pin. See the sequence detail in Figure 35. The μC

can therefore test the deployment times by measuring the duration of the high pulses sent

by the IC on the ARM1 pin. The deployment time configuration used during this test is the

latest one programmed in the DCRx registers. In case the test is run on a channel with no

DCRx deployment time previously configured, a default 8 μs high pulse is output on ARM for

the relevant channel.

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