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L9679P 数据表(PDF) 171 Page - STMicroelectronics |
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L9679P 数据表(HTML) 171 Page - STMicroelectronics |
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171 / 272 page ![]() DocID029275 Rev 1 171/272 L9679P Remote sensor interface 271 9 Remote sensor interface The L9679P contains 2 remote sensor interfaces, capable of supporting PSI-5 protocol (synchronous mode, increased voltage, extended range) . A simplified block diagram of the interface is shown below. The interface supply is given on the SATBUCK pin (refer to Figure 3: Power supply block diagram). The circuitry consists of a power interface that mirrors current flowing in the external sensor and transmits this current information to the decoder, which produces a digital value for each remote sensor channel. The voltage at the RSUx pins can be limited by the power interface in case of SATBUCK supply overvoltage to protect the external sensors. Decoded data are then output through the Remote Sensor Data Registers (RSDRx). Received signals can be processed to the corresponding discrete logic output pin WS0-WS1. The power interface also contains error detection circuitry. When a fault is detected, the error code is stored in a global SPI data buffer in the Remote Sensor Data Registers (RSDRx). Figure 38. Remote sensor interface logic blocks Remote sensor configuration can be addressed via the Remote Sensor Configuration Registers (RSCRx). In particular, TSxDIS bit allows overriding the time slot control for PSI5 I/F and BLKTxSEL allows selection between 5 ms and 10ms for the blanking time applied to the current limitation fault detection each time a channel is activated. The Remote Sensor Control Register (RSCTRL) allows for interface channels to be switched on and off and for Sync Pulse control via SPI. The remote sensor interface reports both data information and fault information in the Remote Sensor Data Register (RSDRx). The device accommodates for a total of 6 data registers. Independent data registers are defined for each remote sensor interface. If the device detects an error on the sensor interface, the MSB in RSDRx (FLTBIT) will be set to '1' and the following bits will be used to report the detected errors. Otherwise, the register will contain only data information. Detailed information on data and fault reporting are explained in the following sections. When a fault condition is detected, the RSFLT bit of the global status word (GSW) is set to 1. Faults other than Short to Ground and Over-temperature will only clear after read, not by the disabling of channel. Data are cleared upon reading the RSDRx register. |
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