L9679P datasheet(185/272 Pages) STMICROELECTRONICS

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L9679P

Watchdog timers

271

To refresh WD2, the logic must receive a WD2_KEY command containing the expected key

value before the WD2 timer expires. If it is received too late the refresh criteria have not

been met. The WD2 error is asserted if the refresh does not occur before the end of the

timeout. The WD2 error is not asserted if it receives continuously a WD2_KEY command

with the correct key. This allows the system software to repeatedly transmit the correct key

value at any rate faster than the required timeout.

Upon reception of the correct key, the logic will generate a new seed value, then calculate a

new key using the new seed and reset the watchdog timer to create a new timeout.

When in WD2 INITSEED state, the three steps above are executed anyway. The seed is

latched from a free-running counter that starts when WSM is released. The WD2_KEY

command is used for transmission of the watchdog key, while WD2_SEED command is

used to read the new seed and the previous key.

The SEED is generated by latching the value from a free-running counter. The free-running

seed counter runs at a rate of fWD2_SEED as specified in Table 29. The key value and seed

value are 8-bits in length. The key shall be calculated as follows: (KEY = SEED ‡ PrevKEY

+ $01) where ‡ denotes a bit-wise XOR operation

10.3

Watchdog reset assertion timer

Upon either a WD1 or a WD2 watchdog reset, the watchdog logic will momentarily assert

the RESET pin for time duration TWDT1_RST / TWDT2_RST. When the RESET pin has been

asserted through the watchdog reset assertion timer, stored faults are maintained and can

be read by the microcontroller via SPI following the RESET period.

10.4

Watchdog timer disable input (WDT/TM)

This input pin has a passive pull-down and is used to disable the watchdog timer. The state

of this pin can be read by SPI through the WDT/TM_S bit in the GSW register. When

WDT/TM pin is asserted, the watchdog timer is disabled, the timer is reset to its starting

value and no faults are generated.

The WDT/TM input pin must not be biased HIGH (WDT/TM > VWDTDIS_TH) prior to POR in

order to have a proper start-up.

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