ADRF6520

Data Sheet

Rev. 0 | Page 24 of 29

SPI REGISTER AND TIMING

The filter frequency, filter bypass mode and offset correction loops can be programmed using the SPI interface. Table 5 provides the bit

map for the internal 24-bit register of the ADRF6520.

Table 5. Bit Map

MSB

LSB

B24

[B23:B9]

B8

[B7:B6]

B5

B4

[B3:B1]

Read/write bit

Address bits

Enable

Don’t care

DC offset disable

Don’t care

Filter frequency code

0: write operation

Set to 000000000010000

0: disable

Don’t care

0: disable

Don’t care

1 dB corner in MHz

1: read operation

1: enable

1: enable

000: 36 MHz

001: 72 MHz

010: 144 MHz

011: 288 MHz

100: 432 MHz

101: 576 MHz

110: 720 MHz

111: bypass

Table 6. Bit Map Default on Power-Up

MSB

LSB

B24

[B23:B9]

B8

[B7:B6]

B5

B4

[B3:B1]

Read/write bit

Address bits

Enable

Don’t care

DC offset disable

Don’t care

Filter frequency code

0

000000000010000

1

Don’t care

1

Don’t care

111