ADRF6520ACPZ-R7 datasheet(20/29 Pages) AD

20 / 29 page

ADRF6520

Data Sheet

Rev. 0 | Page 20 of 29

The RC time constant that, to a first order, dictates the rise and

fall times of the rms output is expressed with the following

equation:

τ (sec) = 500 Ω × (100 pF + CFLTx)

where CFLTx is either the external CFLT1 value or CFLT2 value.

Therefore, for the example of CFLTx = 0 (no external capacitor),

the settling time is 50 ns; and if CFLTx = 1 nF, the settling time is

550 ns. Note that this is the 90% settling time of the rms detector.

There is a slight dependency on input power level, wherein larger

input signals to the rms detector cause it to settle more quickly.

Also, the settling time varies with temperature. The simple

equation, shown previously, is given for guidance so that the

user can set the settling times within an order of magnitude of

where they want it to be. If settling time is important, some

experimentation by the user is necessary to optimize the CFLTx

value for their system.

PROGRAMMABLE FILTERS

The integrated programmable filter is the key signal processing

function in the ADRF6520. The filters follow a four-pole

Butterworth type response that provides minimum in-band

ripple and group delay variation, and good out of band rejection.

The −1 dB bandwidth is programmed from 36 MHz to 720 MHz

in six steps via the SPI, as described in the Programming the

ADRF6520 section. The quoted corner frequency is the −1 dB

point; the ADRF6520 has filter corners at 36 MHz, 72 MHz, 144

MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz.

The filters are designed so that the gain and phase responses vs.

frequency are retained for any bandwidth setting. Figure 66 and

Figure 67 illustrate the ideal four-pole Butterworth response.

The group delay, τG, is defined as

τG = −∂φ/∂ω

where:

φ is the phase in radians.

ω = 2πf is the frequency in radians per second.

Note that for a frequency scaled filter prototype, the absolute

magnitude of the group delay scales inversely with the

bandwidth; however, the shape is retained. For example, the

peak group delay for a 36 MHz bandwidth setting is 20× more

than for a 720 MHz setting.

The corner frequency of the filters is defined by the on-chip

RC product, which can vary by ±20% over manufacturing

variations. Therefore, all the devices are factory calibrated for

corner frequency, resulting in a residual ±8% corner frequency

variation over the −40°C to +85°C temperature range. Although

absolute accuracy requires calibration, the matching of RC

products between the pair of channels is better than 1% by

observing careful design and layout practices. Calibration and

excellent matching ensure that the magnitude and group delay

responses of both channels track together, a critical requirement

for digital IQ-based communication systems.

–160

–140

–120

–100

–80

–60

–40

–20

10M

100M

10G

100G

FREQUENCY (Hz)

36MHz

72MHz

144MHz

288MHz

432MHz

576MHz

720MHz

Figure 66. Ideal Fourth-Order Butterworth Magnitude Response for All 1 dB

Bandwidths Programmed

10M

100M

10G

100G

FREQUENCY (Hz)

36MHz

72MHz

144MHz

288MHz

432MHz

576MHz

720MHz

Figure 67. Ideal Fourth-Order Butterworth Group Delay Response for All 1 dB

Bandwidths Programmed

Bypassing the Filters

For bandwidth applications greater than 720 MHz, the filters of

the ADRF6520 can be bypassed via the SPI. In filter bypass mode,

filters are disabled and power consumption is significantly

reduced. The bandwidth of cascaded VGAs is fully realized in

the filter bypass mode.

VARIABLE GAIN AMPLIFIERS

The second VGA, VGA2, is based on the same architecture as the

input VGA, with 12 dB maximum gain and minimum gain of

−18 dB, providing a 30 dB gain range controlled with a separate

high impedance gain control input, the VGN2 pin. The basic

VGA structure of the second VGA is identical to that of the first

VGA. However, the VGA2 details vary slightly from VGA1 to

produce a higher noise figure.

OUTPUT BUFFERS/ADC DRIVERS

The low impedance (<20 Ω) output buffers of the ADRF6520

have 18 dB of gain and are designed to drive either ADC inputs or

subsequent amplifier stages. They are capable of delivering up to

3.5 V p-p composite two-tone signals into 100 Ω differential

loads with >50 dBc IMD3. The output common-mode of the

ADC driver is set internally to mid supply and cannot be

ADRF6520ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

ADRF6520ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载