ADRF6520ACPZ-R7 datasheet(26/29 Pages) AD

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ADRF6520

Data Sheet

Rev. 0 | Page 26 of 29

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 70 shows the basic connections for a typical ADRF6520

application.

SUPPLY DECOUPLING

Apply a nominal supply voltage of 3.3 V to the supply pins, VPS

and VPSD. The supply voltage must not exceed 3.45 V or drop

below 3.15 V for VPS and VPSD. Decouple each supply pin to

ground with at least one low inductance, surface-mount

ceramic capacitor of 0.1 μF placed as close as possible to the

ADRF6520 device.

The ADRF6520 has two separate supplies: one analog supply

and one digital supply. Take care to separate the analog and

digital supplies with a large surface-mount inductor of 33 μH.

Then decouple each supply separately to its respective ground

through a 10 μF capacitor.

INPUT SIGNAL PATH

Each signal path has an input VGA, accessed through the INP1,

INM1, INP2, and INM2 pins, which sets a differential input

impedance of 100 Ω.

The inputs can be dc-coupled or ac-coupled, but ac coupling is

preferred. There is no mechanism to change the common-mode

voltage; therefore, if the user wants to dc-couple, the common-

mode voltage of the previous stage must match the ADRF6520

input common-mode voltage of 1.375 V.

OUTPUT SIGNAL PATH

The low impedance (20 Ω) output buffers are designed to drive

a 100 Ω impedance load, but can drive larger resistive loads.

The output pins (OPP1, OPM1, OPP2, and OPM2) sit at a

nominal output common-mode voltage of 1.65 V. The outputs

can be dc-coupled or ac-coupled; however, ac coupling is

preferred. There is no mechanism to change the output

common-mode voltage; therefore, if the user wants to dc-

couple, the common-mode voltage of the following stage must

match the ADRF6520 output common-mode voltage of 1.65 V.

DC OFFSET COMPENSATION LOOP ENABLED

When the dc offset compensation loop is enabled via Bit B5 of

the SPI register, the ADRF6520 can null the output differential

dc level. The loop is enabled by setting Bit B5 to 1. The offset

compensation loop creates a high-pass corner frequency, which

is proportional to the value of the capacitors that are connected

from the CHP1 and CHP2 pins to ground. For more

information about setting the high-pass corner frequency, see

the DC Offset Compensation Loop section.

SERIAL PORT CONNECTIONS

The ADRF6520 has a SPI port to control the filter bandwidth,

chip enable, and dc offset compensation loop. Data can be

written to the internal 24-bit register and read from the register.

It is recommended that low-pass RC filtering be placed on the

SPI lines to filter out any high frequency glitches. See the

evaluation board schematic in the ADRF6520-EVALZ user

guide for an example of a low-pass RC filter.

COM

INP2

INM2

INP1

INM1

CFLT1

ADRF6520

VPS

VPSD

VPS

OUTPUT1 (+)

INPUT1 (–)

0.1µF

INPUT1 (+)

INPUT2 (+)

INPUT2 (–)

OUTPUT1 (–)

OUTPUT2 (–)

OUTPUT2 (+)

0.1µF

0.01µF

CFLT2

0.01µF

1nF

VPS

SERIAL

CONTROL

INTERFACE

SERIAL

CONTROL

INTERFACE

1µF

0.1µF

VPSD

VPS

COM

COMD

10µF

33µH

OPP1

OPM1

COM

VGN1

VGN2

COM

OPM2

OPP2

Figure 70. Basic Connections

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