ADRF6520ACPZ-R7 datasheet(21/29 Pages) AD

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Data Sheet

ADRF6520

Rev. 0 | Page 21 of 29

adjusted. If the circuit must be dc-coupled, it must be coupled

to a subsequent stage with matching common mode. However,

if common-mode matching is not possible, take care to limit the

dc common-mode current that is used to shift the common

mode, or else poor linearity results are observed.

DC OFFSET COMPENSATION LOOP

In many signal processing applications, no information is

carried in the dc level. In fact, dc voltages and other low

frequency disturbances can often dominate the intended signal

and consume precious dynamic range in the analog path and

bits in the data converters. These dc voltages can be present

with the desired input signal or can be generated inside the

signal path by inherent dc offsets or other unintended signal-

dependent processes such as self mixing or rectification.

It is recommended to use ac coupling capacitors at the input and

output terminals of the ADRF6520. The ac coupling capacitors

at the input block any dc offset from the input getting into the

device. The coupling capacitors must be sufficiently large,

because they form a high pass filter with the100 Ω differential

input impedance plus any source impedance of the driving circuit.

The high-pass corners may need to be <1 kHz in some cases.

To address the issue of dc offsets generated inside the device, the

ADRF6520 provides a dc offset correction loop that nulls the

output differential dc level, as shown in Figure 68. The correction

loop can be disabled through the SPI port; however, when the

correction loop is disabled, the dc offsets can consume nearly

all of the output dynamic range, especially near maximum gain

settings, because of the large gain of the ADRF6520.

VGN2

FROM

6dB AMP

CHP

CHPx

ENABLE

BIT 5

30dB

VGA

OUTPUT ADC

DRIVER

BASEBAND

OUTPUTS

Figure 68. DC Offset Compensation Loop Operates Around the Second VGA

and ADC Driver

The offset control loop creates a high-pass corner, fHP, that is

superimposed on the normal Butterworth filter response when

filters are enabled. Typically, fHP is many orders of magnitude

lower than the lower programmed filter bandwidth so that there

is no interaction between them. Setting fHP is accomplished with

capacitors, from the CHP1 and CHP2 pins to ground, as shown

in Figure 68. Because the correction loop works around the

VGA sections, fHP is also dependent on the total gain of the

cascaded VGAs.

In general, the expression for fHP is given by

fHP (Hz) = 16.1 × VGA2 Linear Voltage Gain/COFS (µF)

where VGA2 Linear Voltage Gain is expressed in linear terms,

not in decibels (dB), and is the gain following the offset

correction amplifier, which excludes the all prior gain.

For example, the high-pass corner at maximum VGA2 gain,

30 dB, and with COFS = 1 µF, is calculated as follows:

509

)

(

Note that fHP increases in proportion to the gain. For this reason,

choose COFS at the highest operating gain to guarantee that fHP is

always below the maximum limit required by the system.

PROGRAMMING THE ADRF6520

The filter frequency, filter bypass mode, chip enable, and dc offset

correction loop enable are programmed simultaneously through

the SPI port. A 24-bit register stores 8 data bits, 15 bits for

addressing, and 1 bit for a read/write instruction (see Table 5).

The SPI protocol allows these selections to be written into and

read out of the SDIO pin (see the timing diagrams in Figure 69).

The chip select bar (CS) pin must first go to a Logic 0 for a read

or write cycle to begin. On the next rising edge of the clock (SCLK),

a Logic 0 on the SDIO pin initiates a write cycle, whereas a Logic 1

on the SDIO pin initiates a read cycle. In a write cycle, the next

15 SCLK rising edges latch the desired 15-bit address, followed

by the 8-bit data word. The result is a 24-bit code, including the

first Logic 0 to initiate a write cycle. When CS goes high, the write

cycle is completed, and different codes are presented to the filter,

chip enable, and dc offset correction loop enable blocks that

require programming. In a read cycle, after writing in a Logic 1

for the read/write bit and the 15 address bits, the SDIO changes

from an input to an output in the ½ cycle of SCLK between the

last rising edge of SCLK of the instruction (read/write bit and

address bits) and the following falling edge. The next 8 SCLK

rising edges present the stored 8-bit word of data, MSB first on

the SDIO pin. When CS goes high, the read cycle is completed.

Detailed timing diagrams are shown in Figure 69.

NOISE CHARACTERISTICS

The output noise behavior of the ADRF6520 primarily depends

on the gain. Filter corner switching in ADRF6520 is achieved by

changing the on-chip capacitors and keeping the resistors constant,

which results in constant contribution from the filter to the total

noise, irrespective of the filter corner. In filter bypass mode, noise

contribution of the bypass switches is significantly lower than

the active filter, which results in roughly 1 dB lower NF in the

filter bypass mode than the filter mode, at maximum gain.

Each of the VGA sections used in the ADRF6520 contributes a

fixed noise spectral density to its respective output, independent

of the analog gain setting. When cascaded, the total noise

contributed by the VGAs at the output of the ADRF6520

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