ADRF6520ACPZ-R7 datasheet(27/29 Pages) AD

27 / 29 page

Data Sheet

ADRF6520

Rev. 0 | Page 27 of 29

ENABLE/DISABLE FUNCTION

To enable the ADRF6520, pull the ENBL pin high and set the

enable bit in the SPI register (B8) to a logic 1 (by default, the

ADRF6520 powers up with B8 = 1). Either driving the ENBL pin

low or setting B8 = 0 disables the device, reducing current

consumption to approximately 1 mA at room temperature.

GAIN PIN DECOUPLING

The ADRF6520 has two analog gain control pins: VGN1 and

VGN2. Use at least one low inductance, surface-mount ceramic

capacitor with a value of 0.1 µF and one 1000 pF in parallel to

ground on each gain pin to decouple. An example of this can be

seen in the evaluation board schematic in the ADRF6520-

EVALZ user guide.

RMS DETECTOR CONNECTIONS

The ADRF6520 has an rms detector output on the VRMS pin,

with a scaling of 1 V/V rms differential at filter inputs. VRMS

output reports a scaled summation of the differential rms voltage

of both channels: 1 V/V rms × (CH1_RMS + CH2_RMS).

CFLT1 and CFLT2 control the averaging of the Channel 1 and

Channel 2 rms detectors, respectively. The user can leave these

pins open for the fastest response time. The equation relating

the VRMS output video bandwidth and the CFLT1 (or CFLT2)

capacitor is given by

Video BWRMS (Hz) = 0.0007/(130 pF + CFLTx)

where CFLTx is the value of either CFLT1 or CFLT2.

The VRMS pin can source up to 3 mA of current. The output

structure is an NPN emitter follower type, with a 9.5 kΩ resistor

placed from VRMS to ground, internally (see Figure 71). Do

not to load the VRMS output with any load less than 1 kΩ.

VRMS

3mA

MAXIMUM

9.5kΩ

1kΩ

MINIMUM

Figure 71. Simplified Schematic of VRMS Output

VGA2 GAIN STEP RESPONSE

VGA2 gain step response is affected by the dc offset correction

loop. The bandwidth of the loop is set by the value of the CHP1

and CHP2 capacitors. Changing the value of the CHPx capacitors

changes the signature and settling time of VGA2 gain step

response. Figure 62 in the Typical Performance Characteristics

section shows the VGA2 gain step response without the CHPx

capacitor installed. Settling time is approximately 3 µs, and there

are no transient events of any kind while the output settles. This

is not the case when there is a large capacitor placed on CHPx.

Figure 72 shows the VGA2 gain step response with a 1 µF capacitor

placed on CHPx. Settling time is increased to approximately

750 µs, and there is a large transient shift on the output. The user

wants to keep fHP as low as possible to minimize the corruption

of the low frequency spectral information. Care must be taken

when choosing the CHPx capacitor values, to find the correct

balance of the high-pass corner (fHP) imposed on the signal

paths vs. the VGA2 gain step response time. The larger the

CHPx capacitor, the lower fHP corner. The trade-off for lowering

fHP is longer VGA2 gain step response settling times and larger

transient values on the output.

The user must determine what their needs and priorities are for

their application and decide what specifications (fHP vs. VGA2

step response time) to trade-off to satisfy their total system

requirements.

CH2 500mV

CH4 500mV

M500µs

Figure 72. VGA2 Gain Step Response; C9 or C16 = 1 µF

LINEAR OPERATION OF THE ADRF6520

The ADRF6520 has multiple stages per channel. Each stage can

independently be driven into compression depending on the

gain settings and input signal level. There is only access to the

input stages (INP1/INM1 and INP2/INM2) and the output

stages (OPP1/OPM2 and OPP2/OPM2); therefore, the user

must infer the signal level at the input and output of each stage

from the device under test (DUT) input signal level and the

analog gain settings. The maximum recommended signal levels

are shown in Figure 73. Signal levels are presented in units of

V p-p differential, and their equivalent power in dBm re:100 Ω.

OPP1/OPP2

OPM1/OPM2

INP1/INP2

INM1/INM2

VGN1

VGN2

4.0

3.56

3.1

+12

3.56

+12

2.25

3.56

+12

+13

POWER (dBm re: 100Ω)

VOLTAGE (V p-p)

+10.8

Figure 73. Maximum Signal Levels—Single Channel Shown

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